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src/arch/x86/isa/insts/x87/control/save_x87_status_word.py <http://reviews.m5sim.org/r/594/#comment1453> Since FSTSW isn't an instruction it doesn't need to be mentioned. src/arch/x86/isa/insts/x87/control/save_x87_status_word.py <http://reviews.m5sim.org/r/594/#comment1454> This information isn't useful here and shouldn't clutter the instruction definition. src/arch/x86/isa/insts/x87/control/save_x87_status_word.py <http://reviews.m5sim.org/r/594/#comment1455> Reading the status register should automatically fold in the top register. If it doesn't it should. That shouldn't be implemented with microcode. Also, the string constants naming these registers can be set up in arch/x86/isa/microasm.isa by appending them to the "assembler.symbols" dict. Then they'll show up in the scope of the microcode and you can use "rdval t1, fsw" With those changes, there's also no reason to construct the value in a temporary microcode register t1 in the AX case (FNSTSW_R). src/arch/x86/isa/insts/x87/control/save_x87_status_word.py <http://reviews.m5sim.org/r/594/#comment1456> datasize will already be 2 because of the rAw operand. The w is interpreted as "word sized" which means datasize is set to 2 bytes. That's what I remember and what looking at the code seems to confirm, but it's been a while so let me know if you know that's not true. src/arch/x86/isa/operands.isa <http://reviews.m5sim.org/r/594/#comment1452> This is never used and shouldn't be added. src/arch/x86/regs/misc.hh <http://reviews.m5sim.org/r/594/#comment1451> This already exists as MISCREG_FSW. MISCREG_FCW is the control word, and MISCREG_FTW is the tag word. - Gabe On 2011-03-17 16:07:24, Lisa Hsu wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/594/ > ----------------------------------------------------------- > > (Updated 2011-03-17 16:07:24) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > X86: fnstsw: Another patch from Vince Weaver > > > Diffs > ----- > > src/arch/x86/isa/decoder/x87.isa 2e269d6fb3e6 > src/arch/x86/isa/insts/x87/control/save_x87_status_word.py 2e269d6fb3e6 > src/arch/x86/isa/operands.isa 2e269d6fb3e6 > src/arch/x86/regs/misc.hh 2e269d6fb3e6 > > Diff: http://reviews.m5sim.org/r/594/diff > > > Testing > ------- > > > Thanks, > > Lisa > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
