Hi there, I've been facing a situation that I suppose it shouldn't happen. Using the O3 model and SPARC ISA, in the middle of the execution there are some memory operations: Store to address A followed by other accesses to other addresses and then a Load to address A. What happens is that this Load is being somehow flagged as completed before the Store, but reading his data though. I've checked in the Memory Dependency Unit and some other related units but there was nothing I could do there that would change that behavior. And I know that when something like that is detected in the LSQ, it returns a fault, squashes, etc.
As far as I know, the O3 model implements the Alpha Memory Model, and the reordering between memory operations to the same address is not allowed (except in some aggressive implementations, which I think it's not the case). Is this normal and I'm missing something? Or it really shouldn't happen? Thanks in advance, -- Eberle A. Rambo. System Design Automation Lab (LAPS) and Interdepartmental Core of Microelectronics (NIME) Department of Informatics and Statistics (INE) Federal University of Santa Catarina (UFSC) _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
