Lisa should verify, but I think that's what _numCpus is.
On Tue, Apr 19, 2011 at 8:01 AM, Korey Sewell <ksew...@umich.edu> wrote: > Hey Steve, > I dont disagree with your solution (at least in the interim), but > wouldn't the right solution be to have the actual CPUs pass how many > hardware threads is has to the caches? > > The actual "regStats" happens after all the CPUs are instantiated and > ports are connected (right?), so it would seem that since different > CPUs can have a different amount of threads per CPU, that the caches > should just use the port interface to ask "how many threads?" . Then, > the caches down the hierarchy would just sum those thread counts up > for each of their Stat vectors. > > I imagine a similar method to how the "M5 classic" figured out address > ranges and snoop ports would work fine. > > Do people think that's fine or am I missing the point here? > > On Tue, Apr 19, 2011 at 10:42 AM, Steve Reinhardt <ste...@gmail.com> wrote: >> Looks like it's Lisa's fault ;-) >> >> http://repo.m5sim.org/m5/diff/ab05e20dc4a7/src/mem/cache/base.cc >> >> I think Nate's point is that all the stats vector lengths should be >> changed to _numCpus or _numCpus+1 instead of maxThreadsPerCpu to be >> consistent. >> >> We should also either (1) always do _numCpus+1 even though the extra >> "device" slot is unnecessary for SE mode or (2) have a single #ifdef >> to set a local var to one or the other and use that consistently >> rather than having #ifdefs all over the place. I'd lean toward #2 >> just to keep the output a little cleaner in SE mode. >> >> Does that make sense, Lisa? >> >> Steve >> >> On Mon, Apr 18, 2011 at 3:58 PM, nathan binkert <n...@binkert.org> wrote: >>> Yes, but all arithmetic between vectors is elementwise, so they need >>> to be the same length if used in a formula. Total miss latency needs >>> to have the same vector length as total misses. >>> >>> Nate >>> >>> On Mon, Apr 18, 2011 at 2:09 PM, Lisa Hsu <h...@eecs.umich.edu> wrote: >>>> I'm not sure I understand what the problem is either. Can different >>>> VectorStats not have different lengths? >>>> >>>> Lisa >>>> >>>> On Mon, Apr 18, 2011 at 11:43 AM, Gabriel Michael Black < >>>> gbl...@eecs.umich.edu> wrote: >>>> >>>>> My first reaction is "let's fix it", but I don't really understand the >>>>> problem or the impact of changing things. Anything serious? >>>>> >>>>> Gabe >>>>> >>>>> >>>>> Quoting nathan binkert <n...@binkert.org>: >>>>> >>>>> I'm trying to get my python stats stuff committed and I found a bug in >>>>>> the classic cache stats. Look in src/mem/cache/base.cc. The >>>>>> VectorStats have several different lengths "_numCpus + 1", "_numCpus", >>>>>> or "maxThreadsPerCPU". >>>>>> >>>>>> The fact that this works in the current stats package is lucky. I can >>>>>> be bug compatible, but I think we should fix this instead. >>>>>> >>>>>> Nate >>>>>> _______________________________________________ >>>>>> m5-dev mailing list >>>>>> m5-dev@m5sim.org >>>>>> http://m5sim.org/mailman/listinfo/m5-dev >>>>>> >>>>>> >>>>> >>>>> >>>>> _______________________________________________ >>>>> m5-dev mailing list >>>>> m5-dev@m5sim.org >>>>> http://m5sim.org/mailman/listinfo/m5-dev >>>>> >>>>> >>>> _______________________________________________ >>>> m5-dev mailing list >>>> m5-dev@m5sim.org >>>> http://m5sim.org/mailman/listinfo/m5-dev >>>> >>> _______________________________________________ >>> m5-dev mailing list >>> m5-dev@m5sim.org >>> http://m5sim.org/mailman/listinfo/m5-dev >>> >> _______________________________________________ >> m5-dev mailing list >> m5-dev@m5sim.org >> http://m5sim.org/mailman/listinfo/m5-dev >> > > > > -- > - Korey > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
