changeset 6e368a935ac0 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=6e368a935ac0 description: tests: updates for stat name change
diffstat: tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout | 4 +- tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 28 +- tests/long/00.gzip/ref/arm/linux/o3-timing/simout | 4 +- tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt | 28 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/simout | 4 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 28 +- tests/long/00.gzip/ref/x86/linux/o3-timing/simout | 4 +- tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt | 28 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout | 5 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 48 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout | 5 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 28 +- tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout | 4 +- tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 28 +- tests/long/10.mcf/ref/arm/linux/o3-timing/simout | 4 +- tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt | 28 +- tests/long/10.mcf/ref/x86/linux/o3-timing/simout | 4 +- tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt | 28 +- tests/long/20.parser/ref/arm/linux/o3-timing/simout | 4 +- tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt | 28 +- tests/long/20.parser/ref/x86/linux/o3-timing/simerr | 3 +- tests/long/20.parser/ref/x86/linux/o3-timing/simout | 7 +- tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt | 473 ---------- tests/long/30.eon/ref/alpha/tru64/o3-timing/simout | 4 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 28 +- tests/long/30.eon/ref/arm/linux/o3-timing/simout | 4 +- tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt | 28 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout | 4 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 28 +- tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout | 4 +- tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 28 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout | 4 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 28 +- tests/long/50.vortex/ref/arm/linux/o3-timing/simout | 4 +- tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt | 28 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout | 4 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 28 +- tests/long/60.bzip2/ref/arm/linux/o3-timing/simout | 4 +- tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 28 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout | 4 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 28 +- tests/long/70.twolf/ref/arm/linux/o3-timing/simout | 4 +- tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt | 28 +- tests/long/70.twolf/ref/x86/linux/o3-timing/simout | 4 +- tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt | 28 +- tests/quick/00.hello/ref/alpha/linux/o3-timing/simout | 4 +- tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt | 28 +- tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout | 4 +- tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 28 +- tests/quick/00.hello/ref/arm/linux/o3-timing/simout | 4 +- tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt | 28 +- tests/quick/00.hello/ref/mips/linux/o3-timing/simout | 4 +- tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 28 +- tests/quick/00.hello/ref/power/linux/o3-timing/simerr | 2 +- tests/quick/00.hello/ref/power/linux/o3-timing/simout | 4 +- tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt | 28 +- tests/quick/00.hello/ref/x86/linux/o3-timing/simout | 4 +- tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt | 28 +- tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout | 4 +- tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt | 48 +- tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout | 4 +- tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt | 28 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout | 4 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 88 +- 64 files changed, 537 insertions(+), 1010 deletions(-) diffs (truncated from 2397 to 300 lines): diff -r d69720504203 -r 6e368a935ac0 tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Wed Apr 20 19:07:46 2011 -0700 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Fri Apr 22 10:18:51 2011 -0700 @@ -5,8 +5,8 @@ All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:05:54 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:02:50 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff -r d69720504203 -r 6e368a935ac0 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Wed Apr 20 19:07:46 2011 -0700 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Fri Apr 22 10:18:51 2011 -0700 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 385051 # Simulator instruction rate (inst/s) -host_mem_usage 204468 # Number of bytes of host memory used -host_seconds 1468.77 # Real time elapsed on the host -host_tick_rate 110529153 # Simulator tick rate (ticks/s) +host_inst_rate 235652 # Simulator instruction rate (inst/s) +host_mem_usage 207744 # Number of bytes of host memory used +host_seconds 2399.95 # Real time elapsed on the host +host_tick_rate 67644016 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.162342 # Number of seconds simulated @@ -254,16 +254,16 @@ system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 9601978 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 64907 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 10009719 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 24101 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 6020 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11448147 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3134413 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 10009719 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 24101 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 6020 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 11448147 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 3134413 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly diff -r d69720504203 -r 6e368a935ac0 tests/long/00.gzip/ref/arm/linux/o3-timing/simout --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Wed Apr 20 19:07:46 2011 -0700 +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Fri Apr 22 10:18:51 2011 -0700 @@ -5,8 +5,8 @@ All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 12:47:12 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 14:06:31 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff -r d69720504203 -r 6e368a935ac0 tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Wed Apr 20 19:07:46 2011 -0700 +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Fri Apr 22 10:18:51 2011 -0700 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 283332 # Simulator instruction rate (inst/s) -host_mem_usage 214996 # Number of bytes of host memory used -host_seconds 2125.99 # Real time elapsed on the host -host_tick_rate 92433779 # Simulator tick rate (ticks/s) +host_inst_rate 169360 # Simulator instruction rate (inst/s) +host_mem_usage 217476 # Number of bytes of host memory used +host_seconds 3556.69 # Real time elapsed on the host +host_tick_rate 55251704 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 602359865 # Number of instructions simulated sim_seconds 0.196513 # Number of seconds simulated @@ -265,16 +265,16 @@ system.cpu.iew.iewLSQFullEvents 3721 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 12871984 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 65726 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8982 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 25082678 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 87734 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 611520 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15892 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 27153747 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 11966835 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 8982 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 25082678 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 87734 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 611520 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 15892 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 27153747 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 11966835 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 611520 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 628522 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3676919 # Number of branches that were predicted taken incorrectly diff -r d69720504203 -r 6e368a935ac0 tests/long/00.gzip/ref/sparc/linux/o3-timing/simout --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout Wed Apr 20 19:07:46 2011 -0700 +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout Fri Apr 22 10:18:51 2011 -0700 @@ -5,8 +5,8 @@ All Rights Reserved -M5 compiled Apr 19 2011 12:19:46 -M5 started Apr 19 2011 12:20:08 +M5 compiled Apr 21 2011 13:27:10 +M5 started Apr 21 2011 13:30:00 M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff -r d69720504203 -r 6e368a935ac0 tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt Wed Apr 20 19:07:46 2011 -0700 +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt Fri Apr 22 10:18:51 2011 -0700 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 280029 # Simulator instruction rate (inst/s) -host_mem_usage 206320 # Number of bytes of host memory used -host_seconds 5019.49 # Real time elapsed on the host -host_tick_rate 116031336 # Simulator tick rate (ticks/s) +host_inst_rate 154343 # Simulator instruction rate (inst/s) +host_mem_usage 212152 # Number of bytes of host memory used +host_seconds 9107.03 # Real time elapsed on the host +host_tick_rate 63952564 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405604152 # Number of instructions simulated sim_seconds 0.582418 # Number of seconds simulated @@ -243,16 +243,16 @@ system.cpu.iew.iewLSQFullEvents 8462 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 27885594 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 128708 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 40205 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 129748862 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 35905 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 460365 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 237 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 58644458 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 20174020 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 40205 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 129748862 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 35905 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 460365 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 237 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 58644458 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 20174020 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 460365 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 670427 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 5004860 # Number of branches that were predicted taken incorrectly diff -r d69720504203 -r 6e368a935ac0 tests/long/00.gzip/ref/x86/linux/o3-timing/simout --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout Wed Apr 20 19:07:46 2011 -0700 +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout Fri Apr 22 10:18:51 2011 -0700 @@ -5,8 +5,8 @@ All Rights Reserved -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:31:00 +M5 compiled Apr 21 2011 13:30:37 +M5 started Apr 21 2011 13:30:43 M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff -r d69720504203 -r 6e368a935ac0 tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt Wed Apr 20 19:07:46 2011 -0700 +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt Fri Apr 22 10:18:51 2011 -0700 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 229365 # Simulator instruction rate (inst/s) -host_mem_usage 211952 # Number of bytes of host memory used -host_seconds 7069.49 # Real time elapsed on the host -host_tick_rate 106242349 # Simulator tick rate (ticks/s) +host_inst_rate 131052 # Simulator instruction rate (inst/s) +host_mem_usage 215332 # Number of bytes of host memory used +host_seconds 12372.92 # Real time elapsed on the host +host_tick_rate 60703496 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493982 # Number of instructions simulated sim_seconds 0.751079 # Number of seconds simulated @@ -232,16 +232,16 @@ system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 99378480 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 111986 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 30239 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 119484333 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 15966 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6399400 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 47 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 196809249 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 62612798 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 30239 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 119484333 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 15966 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 6399400 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 47 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 196809249 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 62612798 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 6399400 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 4677718 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4430140 # Number of branches that were predicted taken incorrectly diff -r d69720504203 -r 6e368a935ac0 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Wed Apr 20 19:07:46 2011 -0700 +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Fri Apr 22 10:18:51 2011 -0700 @@ -5,12 +5,13 @@ All Rights Reserved -M5 compiled Apr 19 2011 12:17:36 -M5 started Apr 19 2011 12:17:43 +M5 compiled Apr 21 2011 12:02:59 +M5 started Apr 21 2011 13:21:52 M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 109002500 Exiting @ tick 1901725056500 because m5_exit instruction encountered diff -r d69720504203 -r 6e368a935ac0 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt Wed Apr 20 19:07:46 2011 -0700 +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt Fri Apr 22 10:18:51 2011 -0700 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 245660 # Simulator instruction rate (inst/s) -host_mem_usage 294304 # Number of bytes of host memory used -host_seconds 232.36 # Real time elapsed on the host -host_tick_rate 8184534150 # Simulator tick rate (ticks/s) +host_inst_rate 146685 # Simulator instruction rate (inst/s) +host_mem_usage 297796 # Number of bytes of host memory used +host_seconds 389.14 # Real time elapsed on the host +host_tick_rate 4887032789 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 57080594 # Number of instructions simulated sim_seconds 1.901725 # Number of seconds simulated @@ -362,16 +362,16 @@ system.cpu0.iew.iewLSQFullEvents 5675 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.iewSquashCycles 1085015 # Number of cycles IEW is squashing system.cpu0.iew.iewUnblockCycles 526785 # Number of cycles IEW is unblocking -system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 157871 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 427137 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 7542 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 14768 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 12869 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1004382 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 318301 # Number of stores squashed +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.cacheBlocked 157871 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.forwLoads 427137 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.ignoredResponses 7542 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.memOrderViolation 14768 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.rescheduledLoads 12869 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.squashedLoads 1004382 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedStores 318301 # Number of stores squashed system.cpu0.iew.memOrderViolationEvents 14768 # Number of memory order violations system.cpu0.iew.predictedNotTakenIncorrect 331464 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedTakenIncorrect 323527 # Number of branches that were predicted taken incorrectly @@ -978,16 +978,16 @@ system.cpu1.iew.iewLSQFullEvents 5665 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.iewSquashCycles 401676 # Number of cycles IEW is squashing system.cpu1.iew.iewUnblockCycles 76714 # Number of cycles IEW is unblocking -system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
