[m5-dev] changeset in m5: CPU: Add some useful debug message to the timin...

[Ali Saidi]

changeset bfaab04cb292 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bfaab04cb292
description:
        CPU: Add some useful debug message to the timing simple cpu.

diffstat:

 src/cpu/simple/timing.cc |  9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diffs (49 lines):

diff -r 66bb0d8ae8bf -r bfaab04cb292 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc  Wed May 04 20:38:27 2011 -0500
+++ b/src/cpu/simple/timing.cc  Wed May 04 20:38:27 2011 -0500
@@ -729,6 +729,7 @@
         Request *ifetch_req = new Request();
         ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
         setupFetchRequest(ifetch_req);
+        DPRINTF(SimpleCPU, "Translating address %#x\n", 
ifetch_req->getVaddr());
         thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
                 BaseTLB::Execute);
     } else {
@@ -745,8 +746,11 @@
 TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
 {
     if (fault == NoFault) {
+        DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
+                req->getVaddr(), req->getPaddr());
         ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
         ifetch_pkt->dataStatic(&inst);
+        DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
 
         if (!icachePort.sendTiming(ifetch_pkt)) {
             // Need to wait for retry
@@ -758,6 +762,7 @@
             ifetch_pkt = NULL;
         }
     } else {
+        DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", 
req->getVaddr());
         delete req;
         // fetch fault: advance directly to next instruction (fault handler)
         _status = Running;
@@ -800,6 +805,9 @@
 void
 TimingSimpleCPU::completeIfetch(PacketPtr pkt)
 {
+    DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
+            pkt->getAddr() : 0);
+
     // received a response from the icache: execute the received
     // instruction
 
@@ -881,6 +889,7 @@
 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse() && !pkt->wasNacked()) {
+        DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
         // delay processing of returned data until next CPU clock edge
         Tick next_tick = cpu->nextCycle(curTick());
 
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