changeset 2fcad6253525 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2fcad6253525
description:
ARM: Add support for MP misc regs and broadcast flushes.
diffstat:
src/arch/arm/isa.cc | 55 +++++++++++++++++++++++++++++++++++------------
src/arch/arm/miscregs.hh | 6 ++--
2 files changed, 44 insertions(+), 17 deletions(-)
diffs (136 lines):
diff -r ea5a46abdcca -r 2fcad6253525 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Wed May 04 20:38:27 2011 -0500
+++ b/src/arch/arm/isa.cc Wed May 04 20:38:28 2011 -0500
@@ -43,6 +43,7 @@
#include "debug/MiscRegs.hh"
#include "sim/faults.hh"
#include "sim/stat_control.hh"
+#include "sim/system.hh"
namespace ArmISA
{
@@ -191,6 +192,12 @@
miscRegName[misc_reg]);
switch (misc_reg) {
+ case MISCREG_MPIDR:
+ return tc->cpuId();
+ break;
+ case MISCREG_ID_MMFR3:
+ return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
+ // BP Maint | Cache Maint Set/way | Cache Maint MVA
case MISCREG_CLIDR:
warn_once("The clidr register always reports 0 caches.\n");
break;
@@ -244,6 +251,10 @@
{
MiscReg newVal = val;
+ int x;
+ System *sys;
+ ThreadContext *oc;
+
if (misc_reg == MISCREG_CPSR) {
updateRegMap(val);
@@ -351,9 +362,13 @@
return;
case MISCREG_TLBIALLIS:
case MISCREG_TLBIALL:
- warn_once("Need to flush all TLBs in MP\n");
- tc->getITBPtr()->flushAll();
- tc->getDTBPtr()->flushAll();
+ sys = tc->getSystemPtr();
+ for (x = 0; x < sys->numContexts(); x++) {
+ oc = sys->getThreadContext(x);
+ assert(oc->getITBPtr() && oc->getDTBPtr());
+ oc->getITBPtr()->flushAll();
+ oc->getDTBPtr()->flushAll();
+ }
return;
case MISCREG_ITLBIALL:
tc->getITBPtr()->flushAll();
@@ -363,23 +378,35 @@
return;
case MISCREG_TLBIMVAIS:
case MISCREG_TLBIMVA:
- warn_once("Need to flush all TLBs in MP\n");
- tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
- bits(newVal, 7,0));
- tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
- bits(newVal, 7,0));
+ sys = tc->getSystemPtr();
+ for (x = 0; x < sys->numContexts(); x++) {
+ oc = sys->getThreadContext(x);
+ assert(oc->getITBPtr() && oc->getDTBPtr());
+ oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
+ bits(newVal, 7,0));
+ oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
+ bits(newVal, 7,0));
+ }
return;
case MISCREG_TLBIASIDIS:
case MISCREG_TLBIASID:
- warn_once("Need to flush all TLBs in MP\n");
- tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
- tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
+ sys = tc->getSystemPtr();
+ for (x = 0; x < sys->numContexts(); x++) {
+ oc = sys->getThreadContext(x);
+ assert(oc->getITBPtr() && oc->getDTBPtr());
+ oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
+ oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
+ }
return;
case MISCREG_TLBIMVAAIS:
case MISCREG_TLBIMVAA:
- warn_once("Need to flush all TLBs in MP\n");
- tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
- tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
+ sys = tc->getSystemPtr();
+ for (x = 0; x < sys->numContexts(); x++) {
+ oc = sys->getThreadContext(x);
+ assert(oc->getITBPtr() && oc->getDTBPtr());
+ oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
+ oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
+ }
return;
case MISCREG_ITLBIMVA:
tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
diff -r ea5a46abdcca -r 2fcad6253525 src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh Wed May 04 20:38:27 2011 -0500
+++ b/src/arch/arm/miscregs.hh Wed May 04 20:38:28 2011 -0500
@@ -149,6 +149,7 @@
MISCREG_V2POWUR,
MISCREG_V2POWUW,
MISCREG_ID_MMFR0,
+ MISCREG_ID_MMFR3,
MISCREG_ACTLR,
MISCREG_PMCR,
MISCREG_PMCCNTR,
@@ -180,7 +181,6 @@
MISCREG_ID_AFR0,
MISCREG_ID_MMFR1,
MISCREG_ID_MMFR2,
- MISCREG_ID_MMFR3,
MISCREG_AIDR,
MISCREG_ADFSR,
MISCREG_AIFSR,
@@ -230,7 +230,7 @@
"scr", "sder", "par",
"v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
"v2powpr", "v2powpw", "v2powur", "v2powuw",
- "id_mmfr0", "actlr", "pmcr", "pmccntr",
+ "id_mmfr0", "id_mmfr3", "actlr", "pmcr", "pmccntr",
"pmcntenset", "pmcntenclr", "pmovsr",
"pmswinc", "pmselr", "pmceid0",
"pmceid1", "pmc_other", "pmxevcntr",
@@ -240,7 +240,7 @@
// Unimplemented below
"tcmtr",
"id_pfr1", "id_dfr0", "id_afr0",
- "id_mmfr1", "id_mmfr2", "id_mmfr3",
+ "id_mmfr1", "id_mmfr2",
"aidr", "adfsr", "aifsr",
"dcimvac", "dcisw", "mccsw",
"dccmvau",
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