changeset 3c628a51f6e1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3c628a51f6e1
description:
X86: Fix the Lldt instructions so they load the ldtr and not the tr.
diffstat:
src/arch/x86/isa/insts/system/segmentation.py | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diffs (36 lines):
diff -r f64b07758814 -r 3c628a51f6e1
src/arch/x86/isa/insts/system/segmentation.py
--- a/src/arch/x86/isa/insts/system/segmentation.py Thu May 05 02:20:31
2011 -0400
+++ b/src/arch/x86/isa/insts/system/segmentation.py Fri May 06 01:00:32
2011 -0700
@@ -223,8 +223,8 @@
ld t2, tsg, [8, t4, t0], 8, dataSize=8
chks reg, t1, LDTCheck
wrdh t3, t1, t2
- wrdl tr, t1, reg
- wrbase tr, t3, dataSize=8
+ wrdl tsl, t1, reg
+ wrbase tsl, t3, dataSize=8
end:
fault "NoFault"
};
@@ -241,8 +241,8 @@
ld t2, tsg, [8, t4, t0], 8, dataSize=8
chks t5, t1, LDTCheck
wrdh t3, t1, t2
- wrdl tr, t1, t5
- wrbase tr, t3, dataSize=8
+ wrdl tsl, t1, t5
+ wrbase tsl, t3, dataSize=8
end:
fault "NoFault"
};
@@ -260,8 +260,8 @@
ld t2, tsg, [8, t4, t0], 8, dataSize=8
chks t5, t1, LDTCheck
wrdh t3, t1, t2
- wrdl tr, t1, t5
- wrbase tr, t3, dataSize=8
+ wrdl tsl, t1, t5
+ wrbase tsl, t3, dataSize=8
end:
fault "NoFault"
};
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