----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/679/#review1213 -----------------------------------------------------------
Ship it! It looks ok to me, assuming it passes all your tests. - Gabe On 2011-05-04 18:42:58, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/679/ > ----------------------------------------------------------- > > (Updated 2011-05-04 18:42:58) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > ARM: Break up condition codes into normal flags, saturation, and simd. > > This change splits out the condcodes from being one monolithic register > into three blocks that are updated independently. This allows CPUs > to not have to do RMW operations on the flags registers for instructions > that don't write all flags. > > > Diffs > ----- > > src/arch/arm/faults.cc 5a9a639ce16f > src/arch/arm/intregs.hh 5a9a639ce16f > src/arch/arm/isa/formats/fp.isa 5a9a639ce16f > src/arch/arm/isa/formats/pred.isa 5a9a639ce16f > src/arch/arm/isa/insts/data.isa 5a9a639ce16f > src/arch/arm/isa/insts/fp.isa 5a9a639ce16f > src/arch/arm/isa/insts/ldr.isa 5a9a639ce16f > src/arch/arm/isa/insts/macromem.isa 5a9a639ce16f > src/arch/arm/isa/insts/mem.isa 5a9a639ce16f > src/arch/arm/isa/insts/misc.isa 5a9a639ce16f > src/arch/arm/isa/insts/mult.isa 5a9a639ce16f > src/arch/arm/isa/insts/str.isa 5a9a639ce16f > src/arch/arm/isa/operands.isa 5a9a639ce16f > src/arch/arm/isa/templates/pred.isa 5a9a639ce16f > src/arch/arm/miscregs.hh 5a9a639ce16f > src/arch/arm/nativetrace.cc 5a9a639ce16f > > Diff: http://reviews.m5sim.org/r/679/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
