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You need to be careful here since miscregs won't forward results back to later instructions. Anything that depends on the q bit (and by extension the CPSR as a whole) needs to wait for all earlier instructions to complete before executing. I didn't see anything in this change that handles that, but it may have already been in there for some other reason. - Gabe On 2011-05-04 18:43:33, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/680/ > ----------------------------------------------------------- > > (Updated 2011-05-04 18:43:33) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > ARM: Remove the saturating (Q) condition code from the renamed register. > > Move the saturating bit (which is also saturating) from the renamed register > that holds the flags to the CPSR miscreg and adds a allows setting it in a > similar way to the FP saturating registers. This removes a dependency in > instructions that don't write, but need to preserve the Q bit. > > > Diffs > ----- > > src/arch/arm/faults.cc 5a9a639ce16f > src/arch/arm/intregs.hh 5a9a639ce16f > src/arch/arm/isa.cc 5a9a639ce16f > src/arch/arm/isa/insts/data.isa 5a9a639ce16f > src/arch/arm/isa/insts/ldr.isa 5a9a639ce16f > src/arch/arm/isa/insts/macromem.isa 5a9a639ce16f > src/arch/arm/isa/insts/misc.isa 5a9a639ce16f > src/arch/arm/isa/insts/mult.isa 5a9a639ce16f > src/arch/arm/isa/operands.isa 5a9a639ce16f > src/arch/arm/miscregs.hh 5a9a639ce16f > src/arch/arm/nativetrace.cc 5a9a639ce16f > > Diff: http://reviews.m5sim.org/r/680/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
