Hello, I need write combining support. I've looked through the code and I believe that the O3 model and/or cache model does not support it. Is this correct? I've followed a "wmb" assembler command through the simulator and I see where it enforces memory store ordering but I don't see a point where a write buffer would be flushed. How would I go about implementing write combining? At this point I believe that the write buffer would reside in the Cache class but it's not clear to me how a "wmb" command would get to the cache and cause the write buffer to be flushed.
Mike _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
