changeset 3c1296738e34 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3c1296738e34
description:
O3: Fix an issue with a load & branch instruction and mem dep squashing
Instructions that load an address and are control instructions can
execute down the wrong path if they were predicted correctly and then
instructions following them are squashed. If an instruction is a
memory and control op use the predicted address for the next PC instead
of just advancing the PC. Without this change NPC is used for the next
instruction, but predPC is used to verify that the branch was successful
so the wrong path is silently executed.
diffstat:
src/cpu/o3/iew_impl.hh | 12 ++++++++++--
1 files changed, 10 insertions(+), 2 deletions(-)
diffs (22 lines):
diff -r d57afdcf38f5 -r 3c1296738e34 src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh Thu May 12 11:19:35 2011 -0700
+++ b/src/cpu/o3/iew_impl.hh Fri May 13 17:27:00 2011 -0500
@@ -485,8 +485,16 @@
inst->seqNum < toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum;
- TheISA::PCState pc = inst->pcState();
- TheISA::advancePC(pc, inst->staticInst);
+ TheISA::PCState pc;
+ if (inst->isMemRef() && inst->isIndirectCtrl()) {
+ // If an operation is a control operation as well as a memory
+ // reference we need to use the predicted PC, not the PC+N
+ // This instruction will verify misprediction based on predPC
+ pc = inst->readPredTarg();
+ } else {
+ pc = inst->pcState();
+ TheISA::advancePC(pc, inst->staticInst);
+ }
toCommit->pc[tid] = pc;
toCommit->mispredictInst[tid] = NULL;
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