changeset 858384f3af1c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=858384f3af1c
description:
ARM: Break up condition codes into normal flags, saturation, and simd.
This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.
diffstat:
src/arch/arm/faults.cc | 4 ++-
src/arch/arm/intregs.hh | 4 ++-
src/arch/arm/isa/formats/fp.isa | 5 +--
src/arch/arm/isa/formats/pred.isa | 37 ++++++++++++++++-----------------
src/arch/arm/isa/insts/data.isa | 22 ++++++++++---------
src/arch/arm/isa/insts/fp.isa | 15 +------------
src/arch/arm/isa/insts/ldr.isa | 4 +-
src/arch/arm/isa/insts/macromem.isa | 15 +++++++++----
src/arch/arm/isa/insts/mem.isa | 2 +-
src/arch/arm/isa/insts/misc.isa | 41 ++++++++++++++++++++++--------------
src/arch/arm/isa/insts/mult.isa | 4 +-
src/arch/arm/isa/insts/str.isa | 2 +-
src/arch/arm/isa/operands.isa | 8 ++++--
src/arch/arm/isa/templates/pred.isa | 4 +-
src/arch/arm/miscregs.hh | 5 +++-
src/arch/arm/nativetrace.cc | 4 ++-
16 files changed, 94 insertions(+), 82 deletions(-)
diffs (truncated from 516 to 300 lines):
diff -r eb279d6e08a2 -r 858384f3af1c src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc Fri May 13 17:27:00 2011 -0500
+++ b/src/arch/arm/faults.cc Fri May 13 17:27:01 2011 -0500
@@ -107,7 +107,9 @@
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
- tc->readIntReg(INTREG_CONDCODES);
+ tc->readIntReg(INTREG_CONDCODES_F) |
+ tc->readIntReg(INTREG_CONDCODES_Q) |
+ tc->readIntReg(INTREG_CONDCODES_GE);
Addr curPc M5_VAR_USED = tc->pcState().pc();
ITSTATE it = tc->pcState().itstate();
saved_cpsr.it2 = it.top6;
diff -r eb279d6e08a2 -r 858384f3af1c src/arch/arm/intregs.hh
--- a/src/arch/arm/intregs.hh Fri May 13 17:27:00 2011 -0500
+++ b/src/arch/arm/intregs.hh Fri May 13 17:27:01 2011 -0500
@@ -112,7 +112,9 @@
INTREG_UREG0,
INTREG_UREG1,
INTREG_UREG2,
- INTREG_CONDCODES,
+ INTREG_CONDCODES_F,
+ INTREG_CONDCODES_Q,
+ INTREG_CONDCODES_GE,
INTREG_FPCONDCODES,
NUM_INTREGS,
diff -r eb279d6e08a2 -r 858384f3af1c src/arch/arm/isa/formats/fp.isa
--- a/src/arch/arm/isa/formats/fp.isa Fri May 13 17:27:00 2011 -0500
+++ b/src/arch/arm/isa/formats/fp.isa Fri May 13 17:27:01 2011 -0500
@@ -2074,11 +2074,10 @@
cpsrMask.c = 1;
cpsrMask.v = 1;
if (specReg == MISCREG_FPSCR) {
- return new VmrsApsrFpscr(machInst, INTREG_CONDCODES,
+ return new VmrsApsrFpscr(machInst, INTREG_CONDCODES_F,
(IntRegIndex)specReg, (uint32_t)cpsrMask);
} else {
- return new VmrsApsr(machInst, INTREG_CONDCODES,
- (IntRegIndex)specReg, (uint32_t)cpsrMask);
+ return new Unknown(machInst);
}
} else if (specReg == MISCREG_FPSCR) {
return new VmrsFpscr(machInst, rt, (IntRegIndex)specReg);
diff -r eb279d6e08a2 -r 858384f3af1c src/arch/arm/isa/formats/pred.isa
--- a/src/arch/arm/isa/formats/pred.isa Fri May 13 17:27:00 2011 -0500
+++ b/src/arch/arm/isa/formats/pred.isa Fri May 13 17:27:01 2011 -0500
@@ -45,7 +45,7 @@
calcCcCode = '''
if (%(canOverflow)s){
cprintf("canOverflow: %%d\\n", Rd < resTemp);
- replaceBits(CondCodes, 27, Rd < resTemp);
+ CpsrQ = (Rd < resTemp) ? 1 << 27 : 0;
} else {
uint16_t _ic, _iv, _iz, _in;
_in = (resTemp >> %(negBit)d) & 1;
@@ -53,8 +53,7 @@
_iv = %(ivValue)s & 1;
_ic = %(icValue)s & 1;
- CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
- (CondCodes & 0x0FFFFFFF);
+ CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28;
DPRINTF(Arm, "in = %%d\\n", _in);
DPRINTF(Arm, "iz = %%d\\n", _iz);
@@ -71,11 +70,11 @@
canOverflow = 'false'
if flagtype == "none":
- icReg = icImm = 'CondCodes<29:>'
- iv = 'CondCodes<28:>'
+ icReg = icImm = 'CondCodesF<29:>'
+ iv = 'CondCodesF<28:>'
elif flagtype == "llbit":
- icReg = icImm = 'CondCodes<29:>'
- iv = 'CondCodes<28:>'
+ icReg = icImm = 'CondCodesF<29:>'
+ iv = 'CondCodesF<28:>'
negBit = 63
elif flagtype == "overflow":
canOverflow = "true"
@@ -90,9 +89,9 @@
icReg = icImm = 'findCarry(32, resTemp, op2, ~Rn)'
iv = 'findOverflow(32, resTemp, op2, ~Rn)'
else:
- icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodes<29:>)'
- icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodes<29:>)'
- iv = 'CondCodes<28:>'
+ icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesF<29:>)'
+ icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesF<29:>)'
+ iv = 'CondCodesF<28:>'
return (calcCcCode % {"icValue" : icReg,
"ivValue" : iv,
"negBit" : negBit,
@@ -107,11 +106,11 @@
negBit = 31
canOverflow = 'false'
if flagtype == "none":
- icValue = 'CondCodes<29:>'
- ivValue = 'CondCodes<28:>'
+ icValue = 'CondCodesF<29:>'
+ ivValue = 'CondCodesF<28:>'
elif flagtype == "llbit":
- icValue = 'CondCodes<29:>'
- ivValue = 'CondCodes<28:>'
+ icValue = 'CondCodesF<29:>'
+ ivValue = 'CondCodesF<28:>'
negBit = 63
elif flagtype == "overflow":
icVaule = ivValue = '0'
@@ -127,20 +126,20 @@
ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)'
elif flagtype == "modImm":
icValue = 'rotated_carry'
- ivValue = 'CondCodes<28:>'
+ ivValue = 'CondCodesF<28:>'
else:
- icValue = '(rotate ? rotated_carry:CondCodes<29:>)'
- ivValue = 'CondCodes<28:>'
+ icValue = '(rotate ? rotated_carry:CondCodesF<29:>)'
+ ivValue = 'CondCodesF<28:>'
return calcCcCode % vars()
}};
def format DataOp(code, flagtype = logic) {{
(regCcCode, immCcCode) = getCcCode(flagtype)
regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>,
- shift, CondCodes<29:>);
+ shift, CondCodesF<29:>);
op2 = op2;''' + code
immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
- shift, CondCodes<29:>);
+ shift, CondCodesF<29:>);
op2 = op2;''' + code
regIop = InstObjParams(name, Name, 'PredIntOp',
{"code": regCode,
diff -r eb279d6e08a2 -r 858384f3af1c src/arch/arm/isa/insts/data.isa
--- a/src/arch/arm/isa/insts/data.isa Fri May 13 17:27:00 2011 -0500
+++ b/src/arch/arm/isa/insts/data.isa Fri May 13 17:27:01 2011 -0500
@@ -44,11 +44,11 @@
exec_output = ""
calcGECode = '''
- CondCodes = insertBits(CondCodes, 19, 16, resTemp);
+ CondCodesGE = insertBits(0, 19, 16, resTemp);
'''
calcQCode = '''
- CondCodes = CondCodes | ((resTemp & 1) << 27);
+ CondCodesQ = CondCodesQ | ((resTemp & 1) << 27);
'''
calcCcCode = '''
@@ -58,16 +58,15 @@
_iv = %(ivValue)s & 1;
_ic = %(icValue)s & 1;
- CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
- (CondCodes & 0x0FFFFFFF);
+ CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28;
DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
_in, _iz, _ic, _iv);
'''
# Dict of code to set the carry flag. (imm, reg, reg-reg)
- oldC = 'CondCodes<29:>'
- oldV = 'CondCodes<28:>'
+ oldC = 'CondCodesF<29:>'
+ oldV = 'CondCodesF<28:>'
carryCode = {
"none": (oldC, oldC, oldC),
"llbit": (oldC, oldC, oldC),
@@ -102,8 +101,8 @@
secondOpRe = re.compile("secondOp")
immOp2 = "imm"
- regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
- regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
+ regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesF<29:>)"
+ regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesF<29:>)"
def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
buildCc = True, buildNonCc = True, instFlags = []):
@@ -240,9 +239,12 @@
code += '''
SCTLR sctlr = Sctlr;
uint32_t newCpsr =
- cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true,
sctlr.nmfi);
+ cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE,
+ Spsr, 0xF, true, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
- CondCodes = CondCodesMask & newCpsr;
+ CondCodesF = CondCodesMaskF & newCpsr;
+ CondCodesQ = CondCodesMaskQ & newCpsr;
+ CondCodesGE = CondCodesMaskGE & newCpsr;
NextThumb = ((CPSR)newCpsr).t;
NextJazelle = ((CPSR)newCpsr).j;
NextItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC)
diff -r eb279d6e08a2 -r 858384f3af1c src/arch/arm/isa/insts/fp.isa
--- a/src/arch/arm/isa/insts/fp.isa Fri May 13 17:27:00 2011 -0500
+++ b/src/arch/arm/isa/insts/fp.isa Fri May 13 17:27:01 2011 -0500
@@ -235,21 +235,8 @@
decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop);
exec_output += PredOpExecute.subst(vmrsFpscrIop);
- vmrsApsrCode = vmrsEnabledCheckCode + '''
- Dest = (MiscOp1 & imm) | (Dest & ~imm);
- '''
- vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp",
- { "code": vmrsApsrCode,
- "predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" },
- ["IsSerializeBefore"])
- header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop);
- decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop);
- exec_output += PredOpExecute.subst(vmrsApsrIop);
-
vmrsApsrFpscrCode = vmrsEnabledCheckCode + '''
- assert((imm & ~FpCondCodesMask) == 0);
- Dest = (FpCondCodes & imm) | (Dest & ~imm);
+ Dest = FpCondCodes & FpCondCodesMask;
'''
vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp",
{ "code": vmrsApsrFpscrCode,
diff -r eb279d6e08a2 -r 858384f3af1c src/arch/arm/isa/insts/ldr.isa
--- a/src/arch/arm/isa/insts/ldr.isa Fri May 13 17:27:00 2011 -0500
+++ b/src/arch/arm/isa/insts/ldr.isa Fri May 13 17:27:01 2011 -0500
@@ -106,7 +106,7 @@
wbDiff = 8
accCode = '''
CPSR cpsr = Cpsr;
- URc = cpsr | CondCodes;
+ URc = cpsr | CondCodesF | CondCodesQ | CondCodesGE;
URa = cSwap<uint32_t>(Mem.ud, cpsr.e);
URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
'''
@@ -137,7 +137,7 @@
def __init__(self, *args, **kargs):
super(LoadRegInst, self).__init__(*args, **kargs)
self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
- " shiftType, CondCodes<29:>)"
+ " shiftType, CondCodesF<29:>)"
if self.add:
self.wbDecl = '''
MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt,
shiftType);
diff -r eb279d6e08a2 -r 858384f3af1c src/arch/arm/isa/insts/macromem.isa
--- a/src/arch/arm/isa/insts/macromem.isa Fri May 13 17:27:00 2011 -0500
+++ b/src/arch/arm/isa/insts/macromem.isa Fri May 13 17:27:01 2011 -0500
@@ -90,9 +90,12 @@
CPSR cpsr = Cpsr;
SCTLR sctlr = Sctlr;
uint32_t newCpsr =
- cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
+ cpsrWriteByInstr(cpsr | CondCodesF | CondCodesQ | CondCodesGE,
+ Spsr, 0xF, true, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
- CondCodes = CondCodesMask & newCpsr;
+ CondCodesF = CondCodesMaskF & newCpsr;
+ CondCodesQ = CondCodesMaskQ & newCpsr;
+ CondCodesGE = CondCodesMaskGE & newCpsr;
IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
| (((CPSR)Spsr).it1 & 0x3);
@@ -585,7 +588,7 @@
{'code':
'''URa = URb + shift_rm_imm(URc, shiftAmt,
shiftType,
- CondCodes<29:>);
+ CondCodesF<29:>);
''',
'predicate_test': predicateTest},
['IsMicroop'])
@@ -601,7 +604,7 @@
{'code':
'''URa = URb - shift_rm_imm(URc, shiftAmt,
shiftType,
- CondCodes<29:>);
+ CondCodesF<29:>);
''',
'predicate_test': predicateTest},
['IsMicroop'])
@@ -631,7 +634,9 @@
NextJazelle = ((CPSR)newCpsr).j;
NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
| (((CPSR)URb).it1 & 0x3);
- CondCodes = CondCodesMask & newCpsr;
+ CondCodesF = CondCodesMaskF & newCpsr;
+ CondCodesQ = CondCodesMaskQ & newCpsr;
+ CondCodesGE = CondCodesMaskGE & newCpsr;
'''
microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
diff -r eb279d6e08a2 -r 858384f3af1c src/arch/arm/isa/insts/mem.isa
--- a/src/arch/arm/isa/insts/mem.isa Fri May 13 17:27:00 2011 -0500
+++ b/src/arch/arm/isa/insts/mem.isa Fri May 13 17:27:01 2011 -0500
@@ -120,7 +120,7 @@
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