changeset 16911ff780d3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=16911ff780d3
description:
ARM: Construct the predicate test register for more instruction
programatically.
If one of the condition codes isn't being used in the execution we
should only
read it if the instruction might be dependent on it. With the
preeceding changes
there are several more cases where we should dynamically pick instead
of assuming
as we did before.
diffstat:
src/arch/arm/isa/formats/pred.isa | 32 ++++++++++++------------
src/arch/arm/isa/insts/data.isa | 48 ++++++++++++++++--------------------
src/arch/arm/isa/insts/ldr.isa | 2 +-
src/arch/arm/isa/insts/macromem.isa | 27 ++++++++------------
src/arch/arm/isa/insts/mem.isa | 25 +++++++++++++------
src/arch/arm/isa/insts/misc.isa | 8 +++---
src/arch/arm/isa/insts/mult.isa | 12 ++++----
src/arch/arm/isa/insts/str.isa | 2 +-
src/arch/arm/isa/operands.isa | 5 +++
9 files changed, 83 insertions(+), 78 deletions(-)
diffs (truncated from 379 to 300 lines):
diff -r 5a95f1d2494e -r 16911ff780d3 src/arch/arm/isa/formats/pred.isa
--- a/src/arch/arm/isa/formats/pred.isa Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/isa/formats/pred.isa Fri May 13 17:27:02 2011 -0500
@@ -48,10 +48,10 @@
CpsrQ = (Rd < resTemp) ? 1 << 27 : 0;
} else {
uint16_t _ic, _iv, _iz, _in;
- _in = (resTemp >> %(negBit)d) & 1;
+ _in = (resTemp >> %(negBit)d);
_iz = (resTemp == 0);
- _iv = %(ivValue)s & 1;
- _ic = %(icValue)s & 1;
+ _iv = %(ivValue)s;
+ _ic = %(icValue)s;
CondCodesNZ = (_in << 1) | (_iz);
CondCodesC = _ic;
@@ -138,23 +138,23 @@
def format DataOp(code, flagtype = logic) {{
(regCcCode, immCcCode) = getCcCode(flagtype)
regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>,
- shift, CondCodesC);
+ shift, 0);
op2 = op2;''' + code
immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
- shift, CondCodesC);
+ shift, OptShiftRmCondCodesC);
op2 = op2;''' + code
regIop = InstObjParams(name, Name, 'PredIntOp',
{"code": regCode,
- "predicate_test": predicateTest})
+ "predicate_test": pickPredicate(regCode)})
immIop = InstObjParams(name, Name + "Imm", 'PredIntOp',
{"code": immCode,
- "predicate_test": predicateTest})
+ "predicate_test": pickPredicate(imm)})
regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',
- {"code": regCode + regCcCode,
- "predicate_test": condPredicateTest})
+ {"code": regCode + regCcCode,
+ "predicate_test": pickPredicate(regCode +
regCcCode)})
immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp',
- {"code": immCode + immCcCode,
- "predicate_test": condPredicateTest})
+ {"code": immCode + immCcCode,
+ "predicate_test": pickPredicate(immCode +
immCcCode)})
header_output = BasicDeclare.subst(regIop) + \
BasicDeclare.subst(immIop) + \
BasicDeclare.subst(regCcIop) + \
@@ -174,10 +174,10 @@
code += "resTemp = resTemp;"
iop = InstObjParams(name, Name, 'PredImmOp',
{"code": code,
- "predicate_test": predicateTest})
+ "predicate_test": pickPredicate(code)})
ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp',
- {"code": code + getImmCcCode(flagtype),
- "predicate_test": condPredicateTest})
+ {"code": code + getImmCcCode(flagtype),
+ "predicate_test": pickPredicate(code + getImmCcCode(flagtype))})
header_output = BasicDeclare.subst(iop) + \
BasicDeclare.subst(ccIop)
decoder_output = BasicConstructor.subst(iop) + \
@@ -190,7 +190,7 @@
def format PredOp(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'PredOp',
{"code": code,
- "predicate_test": predicateTest},
+ "predicate_test": pickPredicate(code)},
opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
@@ -201,7 +201,7 @@
def format PredImmOp(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'PredImmOp',
{"code": code,
- "predicate_test": predicateTest},
+ "predicate_test": pickPredicate(code)},
opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff -r 5a95f1d2494e -r 16911ff780d3 src/arch/arm/isa/insts/data.isa
--- a/src/arch/arm/isa/insts/data.isa Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/isa/insts/data.isa Fri May 13 17:27:02 2011 -0500
@@ -103,8 +103,8 @@
secondOpRe = re.compile("secondOp")
immOp2 = "imm"
- regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesC)"
- regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesC)"
+ regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, OptShiftRmCondCodesC)"
+ regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, 0)"
def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
buildCc = True, buildNonCc = True, instFlags = []):
@@ -125,12 +125,12 @@
}
immCode = secondOpRe.sub(immOp2, code)
immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
- {"code" : immCode,
- "predicate_test": predicateTest}, instFlags)
+ {"code" : immCode,
+ "predicate_test": pickPredicate(immCode)}, instFlags)
immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
- "DataImmOp",
- {"code" : immCode + immCcCode,
- "predicate_test": condPredicateTest},
instFlags)
+ "DataImmOp",
+ {"code" : immCode + immCcCode,
+ "predicate_test": pickPredicate(immCode + immCcCode)}, instFlags)
def subst(iop):
global header_output, decoder_output, exec_output
@@ -163,15 +163,15 @@
}
regCode = secondOpRe.sub(regOp2, code)
regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
- {"code" : regCode, "is_ras_pop" : isRasPop,
- "is_branch" : isBranch,
- "predicate_test": predicateTest}, instFlags)
+ {"code" : regCode, "is_ras_pop" : isRasPop,
+ "is_branch" : isBranch,
+ "predicate_test": pickPredicate(regCode)}, instFlags)
regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
- "DataRegOp",
- {"code" : regCode + regCcCode,
- "predicate_test": condPredicateTest,
- "is_ras_pop" : isRasPop,
- "is_branch" : isBranch}, instFlags)
+ "DataRegOp",
+ {"code" : regCode + regCcCode,
+ "predicate_test": pickPredicate(regCode + regCcCode),
+ "is_ras_pop" : isRasPop,
+ "is_branch" : isBranch}, instFlags)
def subst(iop):
global header_output, decoder_output, exec_output
@@ -204,14 +204,14 @@
}
regRegCode = secondOpRe.sub(regRegOp2, code)
regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,
- "DataRegRegOp",
- {"code" : regRegCode,
- "predicate_test": predicateTest})
+ "DataRegRegOp",
+ {"code" : regRegCode,
+ "predicate_test": pickPredicate(regRegCode)})
regRegIopCc = InstObjParams(mnem + "s",
- mnem.capitalize() + suffix + "Cc",
- "DataRegRegOp",
- {"code" : regRegCode + regRegCcCode,
- "predicate_test": condPredicateTest})
+ mnem.capitalize() + suffix + "Cc",
+ "DataRegRegOp",
+ {"code" : regRegCode + regRegCcCode,
+ "predicate_test": pickPredicate(regRegCode + regRegCcCode)})
def subst(iop):
global header_output, decoder_output, exec_output
@@ -241,10 +241,6 @@
code += '''
SCTLR sctlr = Sctlr;
CPSR old_cpsr = Cpsr;
- old_cpsr.nz = CondCodesNZ;
- old_cpsr.c = CondCodesC;
- old_cpsr.v = CondCodesV;
- old_cpsr.ge = CondCodesGE;
CPSR new_cpsr =
cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
diff -r 5a95f1d2494e -r 16911ff780d3 src/arch/arm/isa/insts/ldr.isa
--- a/src/arch/arm/isa/insts/ldr.isa Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/isa/insts/ldr.isa Fri May 13 17:27:02 2011 -0500
@@ -141,7 +141,7 @@
def __init__(self, *args, **kargs):
super(LoadRegInst, self).__init__(*args, **kargs)
self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
- " shiftType, CondCodesC)"
+ " shiftType, OptShiftRmCondCodesC)"
if self.add:
self.wbDecl = '''
MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt,
shiftType);
diff -r 5a95f1d2494e -r 16911ff780d3 src/arch/arm/isa/insts/macromem.isa
--- a/src/arch/arm/isa/insts/macromem.isa Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/isa/insts/macromem.isa Fri May 13 17:27:02 2011 -0500
@@ -89,10 +89,6 @@
microRetUopCode = '''
CPSR old_cpsr = Cpsr;
SCTLR sctlr = Sctlr;
- old_cpsr.nz = CondCodesNZ;
- old_cpsr.c = CondCodesC;
- old_cpsr.v = CondCodesV;
- old_cpsr.ge = CondCodesGE;
CPSR new_cpsr =
cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
@@ -588,14 +584,14 @@
'predicate_test': predicateTest},
['IsMicroop'])
+ microAddUopCode = '''
+ URa = URb + shift_rm_imm(URc, shiftAmt, shiftType,
OptShiftRmCondCodesC);
+ '''
+
microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
'MicroIntRegOp',
- {'code':
- '''URa = URb + shift_rm_imm(URc, shiftAmt,
- shiftType,
- CondCodesC);
- ''',
- 'predicate_test': predicateTest},
+ {'code': microAddUopCode,
+ 'predicate_test':
pickPredicate(microAddUopCode)},
['IsMicroop'])
microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
@@ -604,14 +600,13 @@
'predicate_test': predicateTest},
['IsMicroop'])
+ microSubUopCode = '''
+ URa = URb - shift_rm_imm(URc, shiftAmt, shiftType,
OptShiftRmCondCodesC);
+ '''
microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
'MicroIntRegOp',
- {'code':
- '''URa = URb - shift_rm_imm(URc, shiftAmt,
- shiftType,
- CondCodesC);
- ''',
- 'predicate_test': predicateTest},
+ {'code': microSubUopCode,
+ 'predicate_test':
pickPredicate(microSubUopCode)},
['IsMicroop'])
microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
diff -r 5a95f1d2494e -r 16911ff780d3 src/arch/arm/isa/insts/mem.isa
--- a/src/arch/arm/isa/insts/mem.isa Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/isa/insts/mem.isa Fri May 13 17:27:02 2011 -0500
@@ -120,14 +120,21 @@
def pickPredicate(blobs):
opt_nz = True
- opt_c = True
+ opt_c = 'opt'
opt_v = True
- for val in blobs.values():
- if re.search('(?<!Opt)CondCodesNZ', val):
+
+ if not isinstance(blobs, dict):
+ vals = [blobs]
+ else:
+ vals = blobs.values()
+ for val in vals:
+ if re.search('(?<!Opt)CondCodesNZ(?!.*=)', val):
opt_nz = False
- if re.search('(?<!Opt)CondCodesC', val):
- opt_c = False
- if re.search('(?<!Opt)CondCodesV', val):
+ if re.search('OptShiftRmCondCodesC(?!.*=)', val):
+ opt_c = 'opt_shift_rm'
+ elif re.search('(?<!Opt)CondCodesC(?!.*=)', val):
+ opt_c = 'none'
+ if re.search('(?<!Opt)CondCodesV(?!.*=)', val):
opt_v = False
# Build up the predicate piece by piece depending on which
@@ -137,8 +144,10 @@
predicate += 'OptCondCodesNZ, '
else:
predicate += 'CondCodesNZ, '
- if opt_c:
+ if opt_c == 'opt':
predicate += 'OptCondCodesC, '
+ elif opt_c == 'opt_shift_rm':
+ predicate += 'OptShiftRmCondCodesC, '
else:
predicate += 'CondCodesC, '
if opt_v:
@@ -146,7 +155,7 @@
else:
predicate += 'CondCodesV, '
predicate += 'condCode)'
-
+ predicate += '/*auto*/'
return predicate
def memClassName(base, post, add, writeback, \
diff -r 5a95f1d2494e -r 16911ff780d3 src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa Fri May 13 17:27:01 2011 -0500
+++ b/src/arch/arm/isa/insts/misc.isa Fri May 13 17:27:02 2011 -0500
@@ -226,7 +226,7 @@
'''
ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
{ "code": ssatCode,
- "predicate_test": condPredicateTest }, [])
+ "predicate_test": pickPredicate(ssatCode) }, [])
header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
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