changeset fb0e525008c5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=fb0e525008c5
description:
ARM: Fix up stats for previous changes to condition codes
diffstat:
tests/long/00.gzip/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt |
782 +++---
tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt |
12 +-
tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt |
12 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout |
12 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt |
1043 +++++----
tests/long/10.mcf/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt |
757 +++---
tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt |
12 +-
tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt |
12 +-
tests/long/20.parser/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt |
811 +++---
tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt |
12 +-
tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt |
12 +-
tests/long/30.eon/ref/arm/linux/o3-timing/simout |
12 +-
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt |
759 +++---
tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt |
16 +-
tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt |
16 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt |
796 +++---
tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt |
16 +-
tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt |
16 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt |
814 +++---
tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt |
12 +-
tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt |
12 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt |
788 +++---
tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt |
12 +-
tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt |
12 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/simout |
12 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt |
767 +++---
tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt |
16 +-
tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt |
16 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/simout |
10 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt |
661 +++---
tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt |
10 +-
tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt |
10 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt |
12 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt |
12 +-
40 files changed, 4181 insertions(+), 4163 deletions(-)
diffs (truncated from 10052 to 300 lines):
diff -r a624d67b642c -r fb0e525008c5
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Fri May 13 17:27:02
2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Fri May 13 17:29:27
2011 -0500
@@ -1,3 +1,5 @@
+Redirecting stdout to
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing/simout
+Redirecting stderr to
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -5,9 +7,9 @@
All Rights Reserved
-M5 compiled Apr 21 2011 12:05:01
-M5 started Apr 21 2011 14:06:31
-M5 executing on maize
+M5 compiled May 4 2011 13:56:47
+M5 started May 4 2011 13:57:03
+M5 executing on nadc-0364
command line: build/ARM_SE/m5.fast -d
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -42,4 +44,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 196513140500 because target called exit()
+Exiting @ tick 189747670000 because target called exit()
diff -r a624d67b642c -r fb0e525008c5
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Fri May 13
17:27:02 2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Fri May 13
17:29:27 2011 -0500
@@ -1,142 +1,142 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 169360 #
Simulator instruction rate (inst/s)
-host_mem_usage 217476 #
Number of bytes of host memory used
-host_seconds 3556.69 #
Real time elapsed on the host
-host_tick_rate 55251704 #
Simulator tick rate (ticks/s)
+host_inst_rate 210962 #
Simulator instruction rate (inst/s)
+host_mem_usage 262196 #
Number of bytes of host memory used
+host_seconds 2855.31 #
Real time elapsed on the host
+host_tick_rate 66454392 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 602359865 #
Number of instructions simulated
-sim_seconds 0.196513 #
Number of seconds simulated
-sim_ticks 196513140500 #
Number of ticks simulated
+sim_insts 602359850 #
Number of instructions simulated
+sim_seconds 0.189748 #
Number of seconds simulated
+sim_ticks 189747670000 #
Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 75744427 #
Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 81879675 #
Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 1640 #
Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 3832102 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 81880205 #
Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 88398894 #
Number of BP lookups
-system.cpu.BPredUnit.usedRAS 1393010 #
Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts 3891220 #
The number of times a branch was mispredicted
-system.cpu.commit.branches 70828614 #
Number of branches committed
-system.cpu.commit.bw_lim_events 7897771 #
number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits 74615208 #
Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 80130233 #
Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 1670 #
Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 3884107 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 80516162 #
Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 86913734 #
Number of BP lookups
+system.cpu.BPredUnit.usedRAS 1397693 #
Number of times the RAS was used to get a target.
+system.cpu.commit.branchMispredicts 3943213 #
The number of times a branch was mispredicted
+system.cpu.commit.branches 70828611 #
Number of branches committed
+system.cpu.commit.bw_lim_events 15126616 #
number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts 602359916 #
The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 6310 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 86859726 #
The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples 379244728
# Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.588315
# Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.904338
# Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 602359901 #
The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 6307 #
The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 75686006 #
The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples 366955970
# Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.641505
# Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.022822
# Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 123478650 32.56% 32.56% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 123013107 32.44% 65.00% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 59170888 15.60% 80.60% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 18488020 4.87% 85.47% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 17225820 4.54% 90.01% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 14373715 3.79% 93.80% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 7590349 2.00% 95.81% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 8006408 2.11% 97.92% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 7897771 2.08% 100.00% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 118814632 32.38% 32.38% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 123407521 33.63% 66.01% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 52313499 14.26% 80.26% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 12481991 3.40% 83.67% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 20938472 5.71% 89.37% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 13691845 3.73% 93.10% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 7616390 2.08% 95.18% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 2565004 0.70% 95.88% #
Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 15126616 4.12% 100.00% #
Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0
# Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 379244728
# Number of insts commited each cycle
-system.cpu.commit.count 602359916 #
Number of instructions committed
+system.cpu.commit.committed_per_cycle::total 366955970
# Number of insts commited each cycle
+system.cpu.commit.count 602359901 #
Number of instructions committed
system.cpu.commit.fp_insts 16 #
Number of committed floating point instructions.
system.cpu.commit.function_calls 997573 #
Number of function calls committed.
-system.cpu.commit.int_insts 533522691 #
Number of committed integer instructions.
-system.cpu.commit.loads 148952607 #
Number of loads committed
+system.cpu.commit.int_insts 533522679 #
Number of committed integer instructions.
+system.cpu.commit.loads 148952604 #
Number of loads committed
system.cpu.commit.membars 1328 #
Number of memory barriers committed
-system.cpu.commit.refs 219173633 #
Number of memory references committed
+system.cpu.commit.refs 219173627 #
Number of memory references committed
system.cpu.commit.swp_count 0 #
Number of s/w prefetches committed
-system.cpu.committedInsts 602359865 #
Number of Instructions Simulated
-system.cpu.committedInsts_total 602359865 #
Number of Instructions Simulated
-system.cpu.cpi 0.652478 #
CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.652478 #
CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 1356 #
number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 10607.142857
# average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_hits 1342 #
number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 148500
# number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate 0.010324 #
miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses 14 #
number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits 14 #
number of LoadLockedReq MSHR hits
-system.cpu.dcache.ReadReq_accesses 139395234 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13041.881358
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7904.223289
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 139153026 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3158848000 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.001738 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 242208 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 46247 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1548919500
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001406 #
mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 195961 #
number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 1340 #
number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 1340 #
number of StoreCondReq hits
+system.cpu.committedInsts 602359850 #
Number of Instructions Simulated
+system.cpu.committedInsts_total 602359850 #
Number of Instructions Simulated
+system.cpu.cpi 0.630014 #
CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.630014 #
CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 1349 #
number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 10133.333333
# average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_hits 1334 #
number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 152000
# number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate 0.011119 #
miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses 15 #
number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits 15 #
number of LoadLockedReq MSHR hits
+system.cpu.dcache.ReadReq_accesses 138720806 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 13339.905680
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8226.668223
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 138476956 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3252936000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.001758 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 243850 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 46844 #
number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1620703000
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001420 #
mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 197006 #
number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses 1337 #
number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits 1337 #
number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses 69417531 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 17910.212192
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10351.034278
# average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 67926304 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 26708191996 #
number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.021482 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1491227 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1243368 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2565597005
# number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 #
mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 247859 #
number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 4376.771337
# average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 17857.107875
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10359.095668
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 67921343 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 26717590518 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.021553 #
miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1496188 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1248875 #
number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2561939027
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 #
mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 247313 #
number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.596339
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 466.592209 #
Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 2191 #
number of cycles access was blocked
+system.cpu.dcache.avg_refs 464.535408 #
Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 2185 #
number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 9589506
# number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 9582528
# number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 208812765 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 17229.974009 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 9270.687452
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 207079330 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 29867039996 #
number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.008301 #
miss rate for demand accesses
-system.cpu.dcache.demand_misses 1733435 #
number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 1289615 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4114516505
# number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002125 #
mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 443820 #
number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 208138337 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 17224.064370 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 9413.601550
# average overall mshr miss latency
+system.cpu.dcache.demand_hits 206398299 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 29970526518 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.008360 #
miss rate for demand accesses
+system.cpu.dcache.demand_misses 1740038 #
number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1295719 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 4182642027
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002135 #
mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 444319 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 4094.849519 #
Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999719 #
Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 208812765 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 17229.974009
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 9270.687452
# average overall mshr miss latency
+system.cpu.dcache.occ_blocks::0 4094.816119 #
Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.999711 #
Average percentage of cache occupancy
+system.cpu.dcache.overall_accesses 208138337 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 17224.064370
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 9413.601550
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 207079330 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 29867039996 #
number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.008301 #
miss rate for overall accesses
-system.cpu.dcache.overall_misses 1733435 #
number of overall misses
-system.cpu.dcache.overall_mshr_hits 1289615 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4114516505
# number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.002125 #
mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 443820 #
number of overall MSHR misses
+system.cpu.dcache.overall_hits 206398299 #
number of overall hits
+system.cpu.dcache.overall_miss_latency 29970526518 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.008360 #
miss rate for overall accesses
+system.cpu.dcache.overall_misses 1740038 #
number of overall misses
+system.cpu.dcache.overall_mshr_hits 1295719 #
number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 4182642027
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002135 #
mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 444319 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 439722 #
number of replacements
-system.cpu.dcache.sampled_refs 443818 #
Sample count of references to valid blocks.
+system.cpu.dcache.replacements 440221 #
number of replacements
+system.cpu.dcache.sampled_refs 444317 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.849519 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 207082021 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 89315000 #
Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 394264 #
number of writebacks
-system.cpu.decode.BlockedCycles 64227537 #
Number of cycles decode is blocked
-system.cpu.decode.BranchMispred 1274 #
Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved 5983982 #
Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts 722350979 #
Number of instructions handled by decode
-system.cpu.decode.IdleCycles 163737957 #
Number of cycles decode is idle
-system.cpu.decode.RunCycles 138388023 #
Number of cycles decode is running
-system.cpu.decode.SquashCycles 12871984 #
Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts 4747 #
Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles 12891210 #
Number of cycles decode is unblocking
+system.cpu.dcache.tagsinuse 4094.816119 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 206400979 #
Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 88948000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 394697 #
number of writebacks
+system.cpu.decode.BlockedCycles 57854165 #
Number of cycles decode is blocked
+system.cpu.decode.BranchMispred 1286 #
Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved 5859491 #
Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts 711052352 #
Number of instructions handled by decode
+system.cpu.decode.IdleCycles 160285716 #
Number of cycles decode is idle
+system.cpu.decode.RunCycles 140722772 #
Number of cycles decode is running
+system.cpu.decode.SquashCycles 11629973 #
Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts 4744 #
Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles 8093316 #
Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 #
DTB accesses
system.cpu.dtb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
@@ -158,242 +158,242 @@
system.cpu.dtb.write_accesses 0 #
DTB write accesses
system.cpu.dtb.write_hits 0 #
DTB write hits
system.cpu.dtb.write_misses 0 #
DTB write misses
-system.cpu.fetch.Branches 88398894 #
Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 71395519 #
Number of cache lines fetched
-system.cpu.fetch.Cycles 153789076 #
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 942755 #
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 689805737 #
Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 34 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
-system.cpu.fetch.SquashCycles 4451587 #
Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.224919 #
Number of branch fetches per cycle
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