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I think this type of change is necessary for reasonable performance, but the implementation here does pose some issues for any ISA that uses micro-coded instructions (and faults on one). Additionally, if you look at small issue width CPUs this doesn't generally solve the problem. We've re-worked this change to fix the correctness issue and as soon as it goes through a battery of internal tests we can post it for review if that works for everyone. - Ali On 2011-05-24 12:01:29, Lisa Hsu wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/718/ > ----------------------------------------------------------- > > (Updated 2011-05-24 12:01:29) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > Enabled instruction fetch pipelining. > > This patch is from one of our co-ops who has since finished her term, Yasuko > Watanabe. I don't personally know much about it. In the end, I'll push in her > name. Thanks. > > > Diffs > ----- > > src/cpu/o3/fetch.hh 54a65799e4c1 > src/cpu/o3/fetch_impl.hh 54a65799e4c1 > > Diff: http://reviews.m5sim.org/r/718/diff > > > Testing > ------- > > > Thanks, > > Lisa > > _______________________________________________ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
