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This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/725/
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
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copyright: clean up copyright blocks

This is basically to make it easier to run the find_copyrights.py utility 
that's added in the next changeset.  It fixes some consistency of naming.  
(e.g. Advanced Micro Devices -> Advanced Micro Devices, Inc.)


Diffs
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  src/arch/alpha/kgdb.h aa00cee9abb1 
  src/arch/alpha/remote_gdb.cc aa00cee9abb1 
  src/arch/arm/remote_gdb.cc aa00cee9abb1 
  src/arch/generic/debugfaults.hh aa00cee9abb1 
  src/arch/sparc/remote_gdb.cc aa00cee9abb1 
  src/arch/x86/insts/badmicroop.hh aa00cee9abb1 
  src/arch/x86/insts/badmicroop.cc aa00cee9abb1 
  src/arch/x86/isa/formats/nop.isa aa00cee9abb1 
  src/base/random_mt.cc aa00cee9abb1 
  src/base/remote_gdb.cc aa00cee9abb1 
  src/dev/ide_wdcreg.h aa00cee9abb1 
  src/dev/sparc/dtod.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/Arbiter.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/Arbiter.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/MatrixArbiter.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/MatrixArbiter.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/RRArbiter.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/RRArbiter.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/SWAllocator.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/SWAllocator.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/VCAllocator.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/VCAllocator.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/AmpUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/AmpUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/BitlineUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/BitlineUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/Buffer.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/Buffer.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/DecoderUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/DecoderUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/MemUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/MemUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/OutdrvUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/OutdrvUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/PrechargeUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/PrechargeUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/Register.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/Register.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/SRAM.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/SRAM.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/WordlineUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/WordlineUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Clock.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Clock.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Crossbar/Crossbar.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Crossbar/Crossbar.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.cc aa00cee9abb1 
  src/mem/ruby/network/orion/FlipFlop.hh aa00cee9abb1 
  src/mem/ruby/network/orion/FlipFlop.cc aa00cee9abb1 
  src/mem/ruby/network/orion/OrionLink.hh aa00cee9abb1 
  src/mem/ruby/network/orion/OrionLink.cc aa00cee9abb1 
  src/mem/ruby/network/orion/OrionRouter.hh aa00cee9abb1 
  src/mem/ruby/network/orion/OrionRouter.cc aa00cee9abb1 
  src/mem/ruby/network/orion/TechParameter.hh aa00cee9abb1 
  src/mem/ruby/network/orion/TechParameter.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Type.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Wire.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Wire.cc aa00cee9abb1 
  src/sim/fault_fwd.hh aa00cee9abb1 
  src/sim/root.hh aa00cee9abb1 
  src/sim/root.cc aa00cee9abb1 
  src/unittest/unittest.hh aa00cee9abb1 
  src/unittest/unittest.cc aa00cee9abb1 

Diff: http://reviews.m5sim.org/r/725/diff


Testing
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Thanks,

Nathan

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