changeset a81aefcef6f9 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=a81aefcef6f9 description: sparc: merge regr. updates w/last update
diffstat: src/arch/sparc/isa/decoder.isa | 6 +- src/arch/sparc/isa/formats/branch.isa | 5 ++ src/arch/sparc/isa/formats/mem/basicmem.isa | 6 ++ src/arch/sparc/isa/formats/mem/swap.isa | 2 +- src/arch/sparc/isa/formats/mem/util.isa | 26 ++++++++++ src/arch/sparc/mt.hh | 71 +++++++++++++++++++++++++++++ src/arch/sparc/registers.hh | 2 + src/cpu/inorder/cpu.cc | 1 + src/cpu/inorder/inorder_dyn_inst.cc | 19 +++++++ 9 files changed, 134 insertions(+), 4 deletions(-) diffs (274 lines): diff -r ce61b7a13407 -r a81aefcef6f9 src/arch/sparc/isa/decoder.isa --- a/src/arch/sparc/isa/decoder.isa Fri Jun 10 03:45:24 2011 -0400 +++ b/src/arch/sparc/isa/decoder.isa Fri Jun 10 03:49:23 2011 -0400 @@ -141,7 +141,7 @@ IntReg midVal; R15 = midVal = (Pstate<3:> ? (PC)<31:0> : PC); NNPC = midVal + disp; - }}); + }},None, None, IsIndirectControl, IsCall); 0x2: decode OP3 { format IntOp { 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); @@ -1005,7 +1005,7 @@ Rd = PC; NNPC = target; } - }}); + }}, IsUncondControl, IsIndirectControl); 0x39: Branch::return({{ Addr target = Rs1 + Rs2_or_imm13; if (fault == NoFault) { @@ -1025,7 +1025,7 @@ Canrestore = Canrestore - 1; } } - }}); + }}, IsUncondControl, IsIndirectControl, IsReturn); 0x3A: decode CC { 0x0: Trap::tcci({{ diff -r ce61b7a13407 -r a81aefcef6f9 src/arch/sparc/isa/formats/branch.isa --- a/src/arch/sparc/isa/formats/branch.isa Fri Jun 10 03:45:24 2011 -0400 +++ b/src/arch/sparc/isa/formats/branch.isa Fri Jun 10 03:49:23 2011 -0400 @@ -262,6 +262,9 @@ let {{ def doBranch(name, Name, base, cond, code, annul_code, fail, annul_fail, opt_flags): + if "IsIndirectControl" not in opt_flags: + opt_flags += ('IsDirectControl', ) + iop = InstObjParams(name, Name, base, {"code": code, "fail": fail, @@ -289,12 +292,14 @@ return (header_output, decoder_output, exec_output, decode_block) def doCondBranch(name, Name, base, cond, code, opt_flags): + opt_flags += ('IsCondControl', ) return doBranch(name, Name, base, cond, code, code, 'NNPC = NNPC; NPC = NPC;\n', 'NNPC = NPC + 8; NPC = NPC + 4;\n', opt_flags) def doUncondBranch(name, Name, base, code, annul_code, opt_flags): + opt_flags += ('IsUncondControl', ) return doBranch(name, Name, base, "true", code, annul_code, ";", ";", opt_flags) diff -r ce61b7a13407 -r a81aefcef6f9 src/arch/sparc/isa/formats/mem/basicmem.isa --- a/src/arch/sparc/isa/formats/mem/basicmem.isa Fri Jun 10 03:45:24 2011 -0400 +++ b/src/arch/sparc/isa/formats/mem/basicmem.isa Fri Jun 10 03:49:23 2011 -0400 @@ -1,3 +1,5 @@ +// -*- mode:c++ -*- + // Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // @@ -45,6 +47,8 @@ %(BasicExecDeclare)s + %(EACompDeclare)s + %(InitiateAccDeclare)s %(CompleteAccDeclare)s @@ -69,6 +73,8 @@ exec_output = doDualSplitExecute(code, postacc_code, addrCalcReg, addrCalcImm, execute, faultCode, name, name + "Imm", Name, Name + "Imm", asi, opt_flags) + exec_output += EACompExecute.subst(iop); + exec_output += EACompExecute.subst(iop_imm); return (header_output, decoder_output, exec_output, decode_block) }}; diff -r ce61b7a13407 -r a81aefcef6f9 src/arch/sparc/isa/formats/mem/swap.isa --- a/src/arch/sparc/isa/formats/mem/swap.isa Fri Jun 10 03:45:24 2011 -0400 +++ b/src/arch/sparc/isa/formats/mem/swap.isa Fri Jun 10 03:49:23 2011 -0400 @@ -163,7 +163,7 @@ "EA_trunc" : TruncateEA} exec_output = doSplitExecute(execute, name, Name, mem_flags, ["IsStoreConditional"], microParams); - return (header_output, decoder_output, exec_output, decode_block) + return (header_output, decoder_output, exec_output + EACompExecute.subst(iop), decode_block) }}; diff -r ce61b7a13407 -r a81aefcef6f9 src/arch/sparc/isa/formats/mem/util.isa --- a/src/arch/sparc/isa/formats/mem/util.isa Fri Jun 10 03:45:24 2011 -0400 +++ b/src/arch/sparc/isa/formats/mem/util.isa Fri Jun 10 03:49:23 2011 -0400 @@ -260,6 +260,32 @@ } }}; +def template EACompExecute {{ + Fault + %(class_name)s::eaComp(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Addr EA; + Fault fault = NoFault; + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + %(fault_check)s; + + // NOTE: Trace Data is written using execute or completeAcc templates + if (fault == NoFault) { + %(EA_trunc)s + xc->setEA(EA); + } + + return fault; + } +}}; + +def template EACompDeclare {{ + Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; +}}; + // This delcares the initiateAcc function in memory operations def template InitiateAccDeclare {{ Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; diff -r ce61b7a13407 -r a81aefcef6f9 src/arch/sparc/mt.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/arch/sparc/mt.hh Fri Jun 10 03:49:23 2011 -0400 @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2011 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Korey Sewell + * + */ + +#ifndef __ARCH_SPARC_MT_HH__ +#define __ARCH_SPARC_MT_HH__ + +/** + * @file + * + * ISA-specific helper functions for multithreaded execution. + */ + +#include <iostream> + +#include "arch/isa_traits.hh" +#include "base/bitfield.hh" +#include "base/misc.hh" +#include "base/trace.hh" +using namespace std; + +namespace SparcISA +{ + +template <class TC> +inline unsigned +getVirtProcNum(TC *tc) +{ + fatal("Sparc is not setup for multithreaded ISA extensions"); + return 0; +} + + +template <class TC> +inline unsigned +getTargetThread(TC *tc) +{ + fatal("Sparc is not setup for multithreaded ISA extensions"); + return 0; +} + +} // namespace SparcISA + +#endif diff -r ce61b7a13407 -r a81aefcef6f9 src/arch/sparc/registers.hh --- a/src/arch/sparc/registers.hh Fri Jun 10 03:45:24 2011 -0400 +++ b/src/arch/sparc/registers.hh Fri Jun 10 03:49:23 2011 -0400 @@ -77,6 +77,8 @@ const int NumIntArchRegs = 32; const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; +const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; + } // namespace SparcISA #endif diff -r ce61b7a13407 -r a81aefcef6f9 src/cpu/inorder/cpu.cc --- a/src/cpu/inorder/cpu.cc Fri Jun 10 03:45:24 2011 -0400 +++ b/src/cpu/inorder/cpu.cc Fri Jun 10 03:49:23 2011 -0400 @@ -32,6 +32,7 @@ #include <algorithm> #include "arch/utility.hh" +#include "base/bigint.hh" #include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/inorder/resources/resource_list.hh" diff -r ce61b7a13407 -r a81aefcef6f9 src/cpu/inorder/inorder_dyn_inst.cc --- a/src/cpu/inorder/inorder_dyn_inst.cc Fri Jun 10 03:45:24 2011 -0400 +++ b/src/cpu/inorder/inorder_dyn_inst.cc Fri Jun 10 03:49:23 2011 -0400 @@ -35,6 +35,7 @@ #include <string> #include "arch/faults.hh" +#include "base/bigint.hh" #include "base/cprintf.hh" #include "base/trace.hh" #include "config/the_isa.hh" @@ -536,6 +537,14 @@ template Fault +InOrderDynInst::read(Addr addr, Twin32_t &data, unsigned flags); + +template +Fault +InOrderDynInst::read(Addr addr, Twin64_t &data, unsigned flags); + +template +Fault InOrderDynInst::read(Addr addr, uint64_t &data, unsigned flags); template @@ -599,6 +608,16 @@ } #ifndef DOXYGEN_SHOULD_SKIP_THIS + +template +Fault +InOrderDynInst::write(Twin32_t data, Addr addr, + unsigned flags, uint64_t *res); + +template +Fault +InOrderDynInst::write(Twin64_t data, Addr addr, + unsigned flags, uint64_t *res); template Fault InOrderDynInst::write(uint64_t data, Addr addr, _______________________________________________ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev