changeset ac4da9f8ea80 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ac4da9f8ea80 description: sparc: update o3 regressions
diffstat: tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr | 1 - tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout | 18 +- tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt | 851 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr | 1 - tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout | 48 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 3380 +++++----- 6 files changed, 2145 insertions(+), 2154 deletions(-) diffs (truncated from 4476 to 300 lines): diff -r ce8b9a250021 -r ac4da9f8ea80 tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr Fri Jun 10 22:15:32 2011 -0400 +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr Fri Jun 10 22:15:34 2011 -0400 @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff -r ce8b9a250021 -r ac4da9f8ea80 tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout Fri Jun 10 22:15:32 2011 -0400 +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout Fri Jun 10 22:15:34 2011 -0400 @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 13:27:10 -M5 started Apr 21 2011 13:28:40 -M5 executing on maize -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing +gem5 compiled Jun 10 2011 22:06:52 +gem5 started Jun 10 2011 22:07:32 +gem5 executing on zooks +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... @@ -22,4 +18,4 @@ LDTW: Passed STTW: Passed Done -Exiting @ tick 18633000 because target called exit() +Exiting @ tick 19016500 because target called exit() diff -r ce8b9a250021 -r ac4da9f8ea80 tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt Fri Jun 10 22:15:32 2011 -0400 +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt Fri Jun 10 22:15:34 2011 -0400 @@ -1,459 +1,460 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 79158 # Simulator instruction rate (inst/s) -host_mem_usage 209796 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 101982426 # Simulator tick rate (ticks/s) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 19016500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 51742 # Simulator instruction rate (inst/s) +host_tick_rate 68090181 # Simulator tick rate (ticks/s) +host_mem_usage 162768 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18633000 # Number of ticks simulated +system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.numCycles 38034 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 5148 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3432 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 838 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4682 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2465 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 2697 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 5067 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 714 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 5154 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 5154 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 714 # The number of times a branch was mispredicted -system.cpu.commit.branches 3359 # Number of branches committed -system.cpu.commit.bw_lim_events 86 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.BPredUnit.usedRAS 337 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 167 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 4256 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 23684 # Number of instructions fetch has processed +system.cpu.fetch.Branches 5148 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2802 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 7695 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 937 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 4256 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 353 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 29221 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.810513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.905949 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21526 73.67% 73.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3882 13.28% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 537 1.84% 88.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 503 1.72% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 680 2.33% 92.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 525 1.80% 94.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 239 0.82% 95.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 192 0.66% 96.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1137 3.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 29221 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.135353 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.622706 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13502 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6935 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 7417 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 107 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1260 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 23270 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1260 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13958 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 243 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6236 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7103 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 421 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 21729 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 112 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 19486 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40358 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 40358 # Number of integer rename lookups +system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5654 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 629 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 601 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2349 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3050 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1902 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 18598 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 570 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 18016 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3968 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3549 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 95 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 29221 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.616543 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.185129 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 20388 69.77% 69.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 4239 14.51% 84.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1899 6.50% 90.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1712 5.86% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 440 1.51% 98.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 282 0.97% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 168 0.57% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 79 0.27% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 29221 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 26 21.14% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 29 23.58% 44.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 68 55.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13295 73.80% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2920 16.21% 90.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1801 10.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 18016 # Type of FU issued +system.cpu.iq.rate 0.473681 # Inst issue rate +system.cpu.iq.fu_busy_cnt 123 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006827 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 65447 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 23160 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 17101 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 18139 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 30 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 824 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 454 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1260 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 132 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 20254 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 413 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3050 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1902 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 570 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 372 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 553 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 925 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17560 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2852 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 456 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 1086 # number of nop insts executed +system.cpu.iew.exec_refs 4598 # number of memory reference insts executed +system.cpu.iew.exec_branches 3866 # Number of branches executed +system.cpu.iew.exec_stores 1746 # Number of stores executed +system.cpu.iew.exec_rate 0.461692 # Inst execution rate +system.cpu.iew.wb_sent 17276 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 17101 # cumulative count of insts written-back +system.cpu.iew.wb_producers 7938 # num instructions producing a value +system.cpu.iew.wb_consumers 9273 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.449624 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.856034 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 5063 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 5051 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 27481 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.552200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.190718 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 838 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 27978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.542390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.183434 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19704 71.70% 71.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4516 16.43% 88.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1458 5.31% 93.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 763 2.78% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 370 1.35% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 256 0.93% 98.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 290 1.06% 99.55% # Number of insts commited each cycle _______________________________________________ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
