This was working at some point. What happened? Ali
Sent from my ARM powered device On Jun 10, 2011, at 9:14 PM, Korey Sewell <ksew...@umich.edu> wrote: > changeset 9bb24e6edc35 in /z/repo/gem5 > details: http://repo.gem5.org/gem5?cmd=changeset;node=9bb24e6edc35 > description: > sparc: don't use directcntrl branch flag > this flag is only used for early branch resolution in the O3 model (of > pc-relative branches) > but this isnt cleanly working even when the branch target code is added > for sparc. For now, > we'll ignore this optimization and add a todo in the SPARC ISA for future > developers > > diffstat: > > src/arch/sparc/isa/formats/branch.isa | 5 +++-- > 1 files changed, 3 insertions(+), 2 deletions(-) > > diffs (15 lines): > > diff -r a81aefcef6f9 -r 9bb24e6edc35 src/arch/sparc/isa/formats/branch.isa > --- a/src/arch/sparc/isa/formats/branch.isa Fri Jun 10 03:49:23 2011 -0400 > +++ b/src/arch/sparc/isa/formats/branch.isa Fri Jun 10 22:15:32 2011 -0400 > @@ -262,8 +262,9 @@ > let {{ > def doBranch(name, Name, base, cond, > code, annul_code, fail, annul_fail, opt_flags): > - if "IsIndirectControl" not in opt_flags: > - opt_flags += ('IsDirectControl', ) > + #@todo: add flags and branchTarget() for DirectCntrl branches > + # the o3 model can take advantage of this annotation if > + # done correctly > > iop = InstObjParams(name, Name, base, > {"code": code, > _______________________________________________ > gem5-dev mailing list > gem5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
