I am using Ruby memory model. I am not able to figure out how to set the cache line size.
I was trying option cacheline_size but such option doesnt exist. I like to set cache line size of L1 and L2 of ALPHA_SE_MESI_CMP_dir system to 1 word i.e., 4bytes. Is it possible and if so can someone help me out? On Thu, Jun 9, 2011 at 7:00 AM, Abhishek Rawat <[email protected]> wrote: > No, I am not using Ruby. But, I thought Ruby model is not yet integrated to > O3 cores. > > > On Wed, Jun 8, 2011 at 9:28 PM, Nilay Vaish <[email protected]> wrote: > >> On Wed, 8 Jun 2011, Abhishek Rawat wrote: >> >> I have tried the latest versions from both the stable and dev >>> repositories. >>> I am running FS mode and have tried both O3 and timing CPU. I haven't >>> made >>> any changes and I am running PARSEC benchmarks. I have not made any >>> changes >>> to the configuration scripts. The only minor changes I have made are >>> those >>> which were required to support PARSEC. >>> >>> Thanks, >>> Abhishek >>> On Wed, Jun 8, 2011 at 7:13 PM, Nilay Vaish <[email protected]> wrote: >>> >>> On Wed, 8 Jun 2011, Abhishek Rawat wrote: >>>> >>>> Hi, >>>> >>>>> I have been trying to change cache line size (to 128) using that >>>>> option. >>>>> But >>>>> I get following error >>>>> >>>>> fatal: port A size 64, port B size 128 >>>>> Busses don't have the same block size... Not supported. >>>>> @ cycle 0 >>>>> [init:build/ALPHA_FS/mem/ >>>>> bridge.cc, line 99] >>>>> >>>>> I don't think just specifying the cacheline_size on command line would >>>>> work. >>>>> I have also tried setting the block size of system.tol2bus to 128 but I >>>>> still get the above error. I am not sure what I am missing. >>>>> >>>>> Thanks, >>>>> Abhishek >>>>> >>>>> On Wed, Jun 8, 2011 at 6:34 PM, Nilay Vaish <[email protected]> wrote: >>>>> >>>>> On Wed, 8 Jun 2011, prasanth wrote: >>>>> >>>>>> >>>>>> Hi, >>>>>> >>>>>> >>>>>>> I am using MESI_CMP_directory protocol. I would like to change the >>>>>>> cache >>>>>>> block >>>>>>> size in L1 cache and L2 cache to 1 word to simplify some techniques >>>>>>> which >>>>>>> I am >>>>>>> experimenting on. >>>>>>> >>>>>>> For the Classic Memory System, configs/common/CacheConfig.py file >>>>>>> sets >>>>>>> the >>>>>>> block >>>>>>> sizes of L1 and L2 caches. But I wasn't able to find the places to >>>>>>> modify >>>>>>> for >>>>>>> Ruby Memory System. >>>>>>> >>>>>>> In src/mem/ruby/system/Cache.py, Ruby Cache class sets >>>>>>> start_index_bit >>>>>>> which is >>>>>>> related to the cache line size. Is this the one to be modified? >>>>>>> >>>>>>> regards, >>>>>>> >>>>>>> Prasanth >>>>>>> >>>>>>> >>>>>>> There is an option for specifying the cacheline size, namely, >>>>>>> >>>>>> cacheline_size. It defaults to 64 bytes. You can set it on the command >>>>>> line. >>>>>> >>>>>> -- >>>>>> Nilay >>>>>> >>>>>> >>>>>> I would be really surprised if the option would not be working as >>>> this >>>> might be one of the most basic things that anybody would like to change, >>>> though it might be that some thing else also needs to be changed as >>>> well). I >>>> have not used the option ever, so I would have to dig in if there is any >>>> problem. >>>> >>>> Can you provide the details of the gem5 version you are using and >>>> whether >>>> or not you have made any changes? >>>> >>>> >>>> -- >>>> Nilay >>>> _______________________________________________ >>>> gem5-users mailing list >>>> [email protected] >>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>>> >>>> >>> >>> >>> -- >>> -Abhishek >>> >>> Graduate Student >>> Computer Science >>> University of Virginia >>> >>> >>> --------------------------------------------------------------------------------------------------------------------- >>> simplicity is the ultimate sophistication >>> -Leonardo da Vinci >>> >>> >> Are you using Ruby? >> >> >> -- >> Nilay >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > > -- > -Abhishek > > Graduate Student > Computer Science > University of Virginia > > > --------------------------------------------------------------------------------------------------------------------- > simplicity is the ultimate sophistication > -Leonardo da Vinci > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- B Saratchandra Prasanth <http://www.cse.iitd.ernet.in/%7Emcs092094> Graduate-student in Computer Science Dept. of Computer Science & Engineering<http://www.cse.iitd.ac.in/index.shtml> Indian Institute of Technology, Delhi <http://www.iitd.ac.in> New Delhi - 110016 Ph. No. 9555918314
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