Hi, This is a snippet of Exec, TLB and MemoryAccess traces generated for a very simple test program
36679500: system.cpu.dtb: lookup 0x8ffc8, asn 0 -> hit ppn 0x49 36679500: system.ruby.cpu_ruby_ports-port1: Timing access caught for address 0x93dc0 36679500: system.ruby.cpu_ruby_ports-port1: Request found in 0 - 0x7ffffff range 36681000: system.ruby.cpu_ruby_ports-port1: Hit callback needs response 1 36681000: system.physmem: Read of size 4 on address 0x93dc0 data 0xa 36681000: system.ruby.cpu_ruby_ports-port1: Sending packet back over port 36681000: system.ruby.cpu_ruby_ports-port1: Hit callback done! 36679500: system.cpu T0 : @main+48 : ldl r1,16(r15) : MemRead : D=0x000000000000000a A=0x11ff91dc0 1) Virtual and Physical Addresses I looked into some posts related to this topic but didn't understand completely. Can someone explain what is 0x8ffc8? tlb.cc does a virtual address to physical address mapping and this is what is the virtual address it gets to translate, then what was the address printed with cpu exec trace 0x11ff91dc0 2) Memory Accesses Is the memory accessed even if there is a cache hit? When I have multiple load instructions one after other to the same location, for every such load instruction, an access to physical memory is printed in the MemoryAccess trace. I was expecting after first load, data is available in cache and so there wont be a memory access for the data. I am working with caches and need to measure timing information and also check the functionality of a modified cache protocol. How can I make sure that the data hits in cache or there is a miss for a certain instruction? 3) Is there a way to track the protocol state changes happening for an instruction in Ruby Memory system? -- B Saratchandra Prasanth <http://www.cse.iitd.ernet.in/%7Emcs092094> Graduate-student in Computer Science Dept. of Computer Science & Engineering<http://www.cse.iitd.ac.in/index.shtml> Indian Institute of Technology, Delhi <http://www.iitd.ac.in> New Delhi - 110016 Ph. No. 9555918314
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