Hi Nilay,

I'm not sure if this will work for your application, but I've usually followed 
the existing pseudo instructions in taking inputs in fixed registers, rather 
than attempting to do smarter decoding of the instruction.  

I then either (#1) run my application on the simulator, modelling the new 
instruction, or (#2) run it at higher speed on real hardware, and write a 
handler for the undefined-instruction fault and have the handler provide a 
simple functional model of the new instruction.  Being able to do #2 has really 
helped me with debugging, and having the inputs in fixed registers makes #2 
much easier.

 --Tim



-----Original Message-----
From: [email protected] [mailto:[email protected]] On 
Behalf Of Nilay Vaish
Sent: 21 June 2011 21:36
To: gem5 users mailing list
Subject: Re: [gem5-users] Add an X86 pseudo instruction

On Tue, 21 Jun 2011, nathan binkert wrote:

>> I need to add a new instruction which takes an immediate value as operand.
>> This instruction would need to interact with the gem5 simulator like 
>> the checkpoint instruction does. As per my understanding, this means 
>> it would be a pseudo instruction. How can I go about adding such an 
>> instruction?
>
> I suggest just looking at some of the pseudo instructions and see how 
> they work.  You end up having to touch a number of files, but the 
> recipe is pretty straightforward.  The only difference is that you 
> might choose to use a different format since you're taking the 
> immediate instead of using registers.
>

The current implementation of the pseudo instructions make use of the immediate 
value to figure out which pseudo instruction to execute. This means that I 
cannot make use of the same opcode. So, I have to add a new one. I have made 
the following additions to two_byte_opcodes.isa file.

+    0x0E: decode OPCODE_OP_TOP5 {
+        0x00: decode OPCODE_OP_BOTTOM3 {
+            format BasicOperate {
+                0x4: newinst({{
+                            PseudoInst::dosomethingnew(xc->tcBase(), 
IMMEDIATE);
+                        }}, IsNonSpeculative);
+                default: M5InternalError::error(
+                       {{"Unexpected instruction opcode!"}});
+            }
+        }
+    }

This compiles, but I am not sure of the width of the IMMEDIATE field in this 
case. How can I ensure that the immediate field has a length, say, 32-bits.

--
Nilay
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