Hello Everyone, I came across a lot of "Inconsistent DMA transfer state: dmaState = 2 devState = 0" errors with the latest GEM5 version in my full system simulations for workload characterization. Several days ago, I digged into the two source files "src/dev/ide_ctrl.cc" and "src/dev/ide_disk.cc". I found that the errors were due to incomplete/incorrect DMA request abortions in the two files, explained as follows:
(1) For certain reasons, the simulated processor wants to abort a DMA request by calling "IdeDisk::abortDma()" at line 385 of "src/dev/ide_ctrl.cc". At this moment, dmaState = 2 (the "Dma_Transfer" state) and devState = 2 (the "Transfer_Data_Dma" state), which are both correct. (2) In another file "src/dev/ide_disk.cc", "abortDma()" will invoke the function "updateState(ACT_CMD_Error)". Within the function "updateState()", since "devState" is in state "Transfer_Data_Dma" and "action" is equal to "ACT_CMD_Error" at present, the "devState" variable will be set to "Device_Idle_SI" or "Device_Idle_S", leaving the "dmaState" variable unchanged (between line 978 and line 986 in "src/dev/ide_disk.cc"). (3) After (1) and (2), if the IDE controller gets a new DMA request, the "Inconsistent DMA transfer state" panic shows up, because "dmaState" is still 2 but "devState" is not 2 any more. I tried many simple methods in a few days, such as altering the "dmaState" value if "devState" is changed on a call to "abortDma()", but none of them worked. So, I would like to get your help with this tough problem. BTW, this kind of problem shows up only when the memory hierarchy is attached, even though the source code of memory hierarchy models are never changed. Thanks, Leonard
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