On Jul 6, 2011, at 9:53 PM, Meng Dong wrote: > Hi all > My subject is about CMP/SMT hybrid architecture but it seems I haven't made > some progress > > I found that The SPARC architecture in gem5 is a SPARC core and it support SMT > So I want to use two SPARC cores to achieve a basic CMP/SMT hybrid > architecture > Is there anyone know how to do that ? Multi-core SPARC simulation is only supported in syscall emulation (SE) mode. Multi-core/thread support was never completed for full system(FS).
> > Another question is that the tests files in m5/tests/configs like > 03-timing-mp.py tsunami-o3-dual.py > they are multi-processor or dual-processor but I think they are the > multi-cores of O3CPU or Atomic CPU > Is my understand right? If not can you explan that to me ? The prior one is dual o3 cores for SE mode while the latter is dual o3 cores for full system alpha. Al > > Thanks > > -- > Yours,Dongmeng > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
