Hi
I want to use MOESI-directory coherency protocol for in a 8 cores CMP. I
have defined 4 L2's, 4 directories and 4 memory banks as following:
Core0 Core1 Core2 Core3 Core4 Core5 Core6
Core7
|------------| |------------|
|---------------| |---------------|
| |
| |
L2 __ Dir0 L2 __ Dir1 L2 __ Dir2
L2 __ Dir3
|-------------------------|--------------------------|-------------------------------|
|
Memory
I couldn't find any information about bandwidth and latency of L2-directory
link, and want to know it. Now, I have considered bandwidth and latency L2
__ Dir link as L2 ----- L2 link. Is it true?
By the way, I have a question about MOESI-directory protocol. Could you tell
me when a write miss occurs for an address and this address exists in
another cache, why this data read to requested cache and then write
operation is done?
Thank you very much.
Best Regards.
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