Hi, I need to add a pipeline stage in ARM_SE's pipeline. For the inorder model, there are 5 stage (Fetch, Decode, Execute, Memory, Writeback). I need to add another stage between Memory and Writeback stage and then do some optimization in the additional stage.
I haven't get any ideal to start the modification. So far, I made out the ARM_SE simulator, and build a cross compiler for it, and run some benchmark's binary code on the original simulator. Can you give me some suggestion at this point? Thanks, Dan
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