You'll need to choose between changing the number of registers in the ISA or managing the register file yourself and blocking when there isnt enough registers.
In resource_pool.cc, you'll see there is a register file manager in use_def.cc defined to interact with registers. More than likely, you can edit code there or add your new commands in the pipeline model (cpu.cc->createBackEndSked) and figure out a way to enforce the restrictions you are applying in terms of physical register usage. It may be helpful as way to create some stat monitoring which registers are used so you know your compiled code is working. I may have a stat in there already that starts to assist with that (uniqueRegs???) As always, look to gem5.org for documentation on how the inorder model works. Good luck, Korey On Sat, Aug 6, 2011 at 8:06 PM, farshad firouzi <[email protected]>wrote: > Hello, > > For one part of my research I need to analyze the effect of reserving 1-2 > registers of the cpu on performance (IPC). For this purpose I use the > -ffixed-reg option of the gcc for compiling. ( I already check the output > ASM to see if the architectural registers are correctly reserved or not). > Afterwards I simulate the benchmarks (spec2000) using ALPHA_SE inorder > model. The problem is that I didn't see any difference (decrease) of IPC > with reserving two(up to 10 registers) in comparison to original one > (without reserving any registers). I think since the inorder model do not > use the register renaming, the number of actual (physical registers) should > be equal to architectural registers. Thus I should see a different IPC. I > really appreciate any help/idea for describing these phenomenon. Moreover is > there any way for changing the number of registers/issue/ALU in the > configuration file. thanks in advance > > Regards, > > Farshad > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- - Korey
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
