i checked the cpu.icache.overall_access::total for each core & that number is equal to what i have mentioned early
On Sun, Aug 7, 2011 at 9:44 PM, Nilay Vaish <[email protected]> wrote: > On Sun, 7 Aug 2011, biswabandan panda wrote: > > i compared the numbers with instruction fetches to the L1 instruction >> cache >> >> On Sun, Aug 7, 2011 at 9:27 PM, Nilay Vaish <[email protected]> wrote: >> >> On Sat, 6 Aug 2011, biswabandan panda wrote: >>> >>> Plz anyone reply. i am confused totally in terms of these statistics. >>> >>>> >>>> On Fri, Aug 5, 2011 at 10:31 PM, biswabandan panda <[email protected] >>>> >>>>> wrote: >>>>> >>>> >>>> Hi, >>>> >>>>> i ran the benchmark named blackscoles with the 2 core detailed >>>>> model . This is the statistics i was getting for the ROI. >>>>> >>>>> >>>>> >>>>> Without prefetching >>>>> ---------------------------- >>>>> system.cpu0.fetch.CacheLines 61605122 >>>>> # Number of cache lines fetched >>>>> system.cpu1.fetch.CacheLines 57299220 >>>>> # Number of cache lines fetched >>>>> >>>>> >>>>> with prefetching (ghb) >>>>> ------------------------------****--- >>>>> system.cpu0.fetch.CacheLines 185709899 >>>>> # Number of cache lines fetched (order of 10x) >>>>> system.cpu1.fetch.CacheLines 203241772 >>>>> # Number of cache lines fetched (order of 10x) >>>>> >>>>> Similarly more misses to L2 . The # Number of cache lines fetched = >>>>> # >>>>> Number of accesses to instruction cache >>>>> >>>>> Could someone tell me what's the reason behind this which causes this >>>>> increase in instruction fetches. >>>>> >>>>> >>>>> How do you know that these are instruction fetches? >>> >>> > You still have not provided enough information. > > > -- > Nilay > ______________________________**_________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> > -- *thanks®ards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/
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