Hi, I have a question about the files that implement Ruby model. I have used from MESI_CMP_directory cache coherence protocol. In the files that implementĀ caches ( slicc description ), there is a structure which its name is TBE.For each write or read from cache, one entry of this strucute is allocated and deallocated. I searched for TBE, but I didn't find any documentation for this structure. Could you tell me what TBE structure do in cacheĀ implemetation? what is difference between cache entry and TBE entry?
thanks, Saeedeh
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
