Most instructions that are branches are marked with the isControl or
isCond/UncondBranch flags. In some cases this isn't done because the
instructions are rather rare and using them as branches is deprecated.
POP and other similar LDM like instructions are created by the MacroMemOp
constructor in src/arch/arm/insts/macromem.cc. These will be marked as
IsControl.
Ali
On Aug 9, 2011, at 12:59 PM, Andrew Lukefahr wrote:
> Hi,
>
> How would I determine the destination registers for ARM's pop instructions in
> M5? Apparently they get mapped to the 'ArmMacroMemoryOp' macro instruction,
> but it doesn't report as having any destination registers. Can I get the
> destination register from the MicroOp? If so, how would I do that?
>
> This is what I had been doing to detect branches:
>
> StaticInstPtr op = StaticInst::decode(machInst, pc.pc() );
> if (op->getName().at(0) == 'b'){ branch = true; dprintf("branch @0x%lx\n",
> pc.pc());}
> else {
> for (int i = 0; i < op->numDestRegs(); i++){
> if (op->destRegIdx(i) == 15) { branch = true; dprintf("implicit
> branch @ 0x%lx\n", pc.pc() ); }
> }
> }
>
> Thanks
>
> Andrew Lukefahr
> [email protected]
>
> Open Source, Open Minds
> _______________________________________________
> gem5-users mailing list
> [email protected]
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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