Most? Ali
On Aug 22, 2011, at 11:35 AM, Richard Strong wrote: > Updating gem5 to the current version appears to have removed most of the > errors. Thanks for the tip. > > Best, > -Rick > > On Fri, Aug 19, 2011 at 3:33 PM, Ali Saidi <[email protected]> wrote: > Hi Rick, > > I just committed a fix that addresses an issue I found with newer kernels and > our ide disk, but I haven't seen this one. It's possible that they're > related, so you might want to try it. > > Ali > > > > > On Fri, 19 Aug 2011 11:03:39 -0700, Richard Strong <[email protected]> > wrote: > >> Hi all, >> >> I was doing an experiment with the Berkeley DB benchmark ex_tpc. What I >> notice is that increasing the disk latency from 1us to 10us causes the >> following: panic in a vanilla kernel: >> >> panic: Inconsistent DMA transfer state: dmaState = 2 devState = 0 >> >> In addition, I notice that if I bind network and disk interrupts to a core, >> this error occurs in twice as many cases. The tested simulation featured two >> m5 default setting O3 cores (I have also seen the same DMA problem with >> simpler O3 models and the TimingSimpleCPU), the vanilla 2.6.27 m5 kernel >> and a 3 level cache (using the MESI express snoop protocol). I am currently >> running gem5-changeset:8339. >> >> I have also found this thread which seems to have a similar problem, but >> considers the x86 ISA and mentions that the APIC is the heart of the problem. >> >> http://www.mail-archive.com/[email protected]/msg03192.html >> >> If anyone happens to know how to fix the problem or efficient documentation >> on how Ide works, your thoughts and words would be greatly appreciated. >> >> Thanks, >> -Rick >> > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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