Hi Dibakar, You'll need to just make something up that works and provides enough bits in each interrupt register to support 128 cores. There is no magic formula. You'll also need to make the complimentary changes to the kernel, palcode, and src/dev/alpha/(backdoor|tsunami_cchip).*.
Ali On Aug 22, 2011, at 9:11 AM, Dibakar Gope wrote: > Hi, > I am trying to simulate more than 64 processors in M5 (ALPHA FS mode). As of > now, I could run the M5 simulations with upto 64 procs with necessary changes > in vmlinux kernel and updated BIG_TSUNAMI supported tsb_osfpal. In order to > obtain the updated tsb_osfpal, I used the changeset in Makefile and > platform.S (system/alpha/palcode, changeset given in > http://www.mail-archive.com/[email protected]/msg10402.html) and > cross-compiled them. However now I need to run simulations on more than 64 > procs. I cross-compiled the vmlinux kernel (2.6.27) with NR_CPUs set to 128 > and BIG_TSUNAMI set to yes. However, Soon after starting the simulation, a > continuous stream of "warn: clear IPI for CPU=#, but NO IPI" warning messages > are printed to the screen. From the prior post on that, it seems an issue > with the tsb_osfpal pal code (as it supports upto 64 procs). So I was trying > to change the config in Makefile and platform.S (system/alpha/palcode) to > make it compatible for 128, but in platfo rm > .S file, I could not figure out all the chnages I should make, for example in > system/alpha/palcode/platform_m5.S, > (changeset given in > http://www.mail-archive.com/[email protected]/msg10402.html) > @@ -71,6 +71,26 @@ > #define osfpcb_q_Ksp pcb_q_ksp > #define pal_impure_common_size ((0x200 + 7) & 0xfff8) > > +#ifdef BIG_TSUNAMI > +#define MAXPROC 0x3f -------------> changed to 0x7f > +#define IPIQ_addr 0x800 -------------> what will be the new value > for 128 procs??? > +#define IPIQ_shift 0 > +#define IPIR_addr 0x840 -------------> new value for 128 procs??? > +#define IPIR_shift 0 > +#define RTC_addr 0x880 -------------> new value for 128 procs??? > +#define RTC_shift 0 > +#define DIR_addr 0xa2 -------------> new value for 128 procs??? > What should be the new values for those IPIQ_addr, IPIR_addr and DIR_addr in > order to support 128 procs? Are their any additional chages I should make in > the remaining code of the platform_m5.S? Could you please provide me with > some information/detail in making those changes in platform.S? Ali might give > me some pointers, as he made the prior changes in palcode. > Thanks! > Dibakar Gope > Graduate Student, UW-Madison > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
