Thanks for your response. Could I disable L1 cache to use directly the share L2 cache? lyh
At 2011-09-07 22:51:21,"Philip Garcia" <[email protected]> wrote: just modify the code where requests are injected (the interface classes) for either opal or ruby to change the mapping of where data goes. You'll likely want a machanism similar to that which is (or maybe was) used in Ruby to handle SMT processors so that you know where to forward memory requests after Ruby, but that's pretty easy to add. Phil On Sep 7, 2011, at 4:38 AM, lyh wrote: Dear all, Now for GEM5, a multi-core CMP or multiple socket SMP can be simulated. The L1 is private at default. If I want to study a share L1 cache architecture for CMP or SMP, how do I configure? Thanks a lot, lyh _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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