You certainly can build a configuration where the CPUs are directly connected to a shared bus that is attached to a shared L1 cache. Whether or not that works will depend on the CPU model you are using and possibly the ISA. There are issues with the O3 model when it doesn't have separate I & D caches.
Steve On Sat, Sep 17, 2011 at 4:54 PM, Gabriel Michael Black < [email protected]> wrote: > I don't think there's any mechanism to do that right now. Other people know > more about the memory system than I do and may know of some way, but as far > as I know there isn't one. > > Gabe > > > Quoting lyh <[email protected]>: > > Hello, >> Could I disable L1 cache to use directly the share L2 cache? >> >> Best regards. >> lyh >> > > > > ______________________________**_________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> >
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