Hi All, I would like to add some new processor model with existing X86 4 core system. For example, I want integrate a new video decoding engine (HW) that works cycle-by-cycle simultaneously with the 4 core x86 CMP; how ever they might share the network on chip and memory subsystem.
Can you please sugges what might be best way to implement such HW model with the existing GEM5 code base? Thanks, Nil _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
