hi,
> Recently I am researching the memory system in M5. I see the
> cache modules send the request, then bus responses from trace infomation,
> but I don't know who schedual that.
> I guess maybe it's the eventqueue who does the schedule, but from
> source code I still can not find clues. Could anyone tell me where I can
find a
> entry point. What files should I focus on to solve the schedule problem
I would appreciate of any advice
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