Hello, I am trying to connect Acquire/Release instructions to the protocol, and I want to change the states of multiple cache lines at once upon Acquire/Release instructions.
1. I was thinking of changing the states of cache lines in Sequencer.C instead of sending multiple requests to the L1 controller. I was wondering if it is possible and if changing the states in the sequencer should be avoided for any reason. I read that I should not add any modification which makes the sequencer dependable on a specific protocol, and I am afraid I am violating the rule (or recommendation?). 2. If I am not allowed to change the states in the sequencer, I am going to first stall the processor, and then walk through the L1 cache to send Acquire requests to every cache line of L1. After finishing all the necessary state changes, then I will unstall the processor and let the simics handle the next instruction. Is there anyone who did similar work before? Does it sound feasible? Any comment/advice would be highly appreciated. Thank you. Best Regards, Ray
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