Try to increase the no of MSHRS and their targets On Sun, Oct 30, 2011 at 12:15 AM, shu <[email protected]> wrote:
> Hi all, > > I am trying to simulate 64 cores in ALPHA_FS module. I got a error when > start to simulate: > > -------------------------------------------------------------------- > > **** REAL SIMULATION **** > info: Entering event queue @ 0. Starting simulation... > panic: Need to implement cache resending nacked packets! > @ cycle 200167000 > [recvTiming:build/ALPHA_FS/mem/cache/cache_impl.hh, line 1639] > Memory Usage: 2527796 KBytes > Program aborted at cycle 200167000 > Aborted (core dumped) > > -------------------------------------------------------------------- > > My command is : ./build/ALPHA_FS/gem5.opt configs/example/fs.py -d -n 64 > --caches --l2cache --l1i_size=8kB --l1d_size=8kB --l2_size=256kB > --num-l2caches=64 > I simulated 16 cores successfully. If I update cores number to 18 or more, > it will doesn't work. > > Could you please help me what I missed? > > Thanks in advance, > Shu. > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- *thanks®ards * *BISWABANDAN*
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