I am Meeran, a ME student from India. I am doing a research project in multicore architectures which involves system bus bandwidth partitioning between cores of the processors. For this i have to design a processor architecture from scratch and go on to reach main memory via L2 cache. Is it possible to design my own processor model in gem5. Is it possible to simulate L2 cache and sytem bus in gem5. Becuase i have to implement a bus of variable bandwidth (2 GB/s to 24GB/s) to study the impact of bandwidth congestion between main memory and L2. Also i have to implement a token ring scheme between the L2 cache and the main memory to control the burstiness of the requests. Is it possible to design all these functionalities in gem5.
Please help me. Regards.
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