Hello,
I am using gem5 simulating ALPHA processor in SE mode. We are using
ruby memory model and hence code in src/mem/ruby/system/MemoryControl.cc to
simulate the main memory latency.
As per my understanding, the memory request service latency is captured
in the code through "bank_busy_time" parameter (apart from the
"mem_ctl_latency" accounting for queuing and stuff) which for DDR-800 is 22
memory cycles. Also the "mem_bus_cycle_multiplier" (default value 5 for
2GHz processor and DDR-800 RAM) parameter which corresponds to the number
of processor cycles per memory cycle. From the code it looks like the
MemoryController is wokenup for every "mem_bus_cycle_multiplier" which is
for every 5 processor cycles there by accounting to the latency in
processor cycles.
However, from our several experiments conducted for 1billion
instructions we do not see much change in the IPC as this bank_busy_time
(indicating the memory latency) is varied from 22 memory cycles to 8
memory cycles show the results below ..
The experimental setup details:
CPU Clock -> 2 GHz
ALPHA_MOESI_hammer configuration
Private L1/L2 caches
8 GB RAM
Benchmarks: SPEC CPU 2006 (like mcf,bzip2 etc)
For bzip2 running 1 Billion instructions
IPC observed
for bank_busy_time of 22 memory cycles : 0.148147721
for bank_busy_time of 8 memory cycles : 0.148200532
Can someone please explain if there is bug in the code or am I missing
something ?
Regards,
Jagadish.
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