NO it does not On 11/12/11, Huxing Zhang <[email protected]> wrote: > Hi All, > > I am using m5 release 2.0_beta6 to run spec CPU 2006 benchmarks. > I find that all caches in m5 must have the same line size. > For example, in a simplest case, a single AtomicCPU has a private L1 > cache with 64B line size. If I change the L2 cache line size to 128B, > the program will fail when writing back a packet from L1 cache to L2 > cache. The error message is as follows: > > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 > **** REAL SIMULATION **** > warn: Entering event queue @ 0. Starting simulation... > warn: Increasing stack size by one page. > m5.debug: build/ALPHA_SE/mem/cache/cache_impl.hh:312: bool > Cache<TagStore>::access(Packet*, typename TagStore::BlkType*&, int&, > PacketList&) [with TagStore = LRU]: Assertion `blkSize == > pkt->getSize()' failed. > > Program received signal SIGABRT, Aborted. > 0x0000003c8e230265 in raise () from /lib64/libc.so.6 > > I am wondering if there is any way for m5 to support different cache > line size in different cache levels? > > Any suggestions are appreciated. > Thanks very much! > > -- > Best Regards, > Huxing > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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