Hi.. I have configured an Alpha system as below..... # scons build/ALPHA_FS/gem5.opt PROTOCOL=MOESI_CMP_directory RUBY=true #./build/ALPHA_FS/gem5.opt configs/example/ruby_fs.py -n 2 --l1i_size=16kB --l1d_size=16kB --l2_size=2MB --num-l2caches=1 --topology=Pt2Pt --timing
Since i am a newbie to Gem5. I have one doubt in modifying the memory controller in ruby. My first doubt in ALPHA architecture is where exactly the role of /src/mem/ruby/system/memorycontrol.cc takes place. what i mean is... whether it dispatches only requests coming from L2 cache miss and direct it to main memory. (i.e implemented off-chip after L2 according to my above specification). (Or) It dispatches memory coming from the core and direct it to L1 cache and forward systematically according to memory hierarchy. Please forgive my ignorance and please help me.... Thank you... _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
