Hello All,
I am trying to more accurately model the memory system for the ARM ISA
(running Android) as well as implement some of the ARM cache flushing
instructions. One problem i'm running into is that the icache contains
dirty data. Looking at the code in cache_impl.hh I see that when a read
request from the L1 cache is satisfied by the L2 cache, and the block is
dirty in the L2, the L2 cache passes the block to the L1 in modified state.
I changed the code in satisfyCpuSideRequest (around line 220) to:
if (blk->isDirty() && (deferred_response || isTopLevel)) {
pkt->assertShared();
}
Essentially, this gets rid of the code to assertMemInhibit and clear the
dirty bit in the L2's block. This works fine and I am still able to boot
Android and run my workload. However, I read in a previous thread that this
could allow the code in the L1 to silently move from E to M state thus
causing the block to be in M state in both caches. This is because the
block is marked as writable in the handleFill code around line 1117.
Instead of doing this should I just add code in the handleFill function
that checks if the cache is the icache, and if so, prevent it from marking
the block as writable and dirty? Or is what I have already done safe?
Thanks,
Anthony
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