It works without issue. Are you using FS or SE? The best way to do this is generally to recompile the program with a m5chechkpoint instruct placed where detailed simulation should begin. You can then restore from this checkpoint to run your simulation.
Ali On Nov 23, 2011, at 12:21 PM, Rio Xiangyu Dong wrote: > I’ve seen some unusual behavior when gem5 is simulating 4 processes on a > 4-core configuration. > > For example, the simulation exits after the fast-forward and reports “Exiting > @ tick xxx because a thread reached the max instruction count”. However, the > program under simulation should still at least 10^9 instructions to run. > To workaround this, I had to increase the fast-forward cycles, and enter the > real simulation mode by manually pushing “Ctrl-C”. The simulation switches > at almost the same location. > > I checked the gem5 wiki page (http://www.gem5.org/Supported_Architectures), > and it says: > “ARM -- Bare metal & Linux single core support with both detailed and simple > CPU models. MP support in progress.” > So, I would like to know if there is any known issues about the ARM MP > support. > > Thank you! > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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