Hi Malek, [CC to gem5 users]
I did have an issue with parts of the system draining correctly. From what I remember though, I actually didn't have to alter anything to do with the draining after all.
The main problem was that I needed to connect the caches to the swapped-in CPU, but that swapped-in CPU already thought it was connected. In your case that would be the Atomic CPU. Since it's already been connected to the caches, you need to force it to reconnect because it doesn't disconnect properly when you swap it out (the caches get reconnected to the Timing CPU but only the caches see the change).
Does that make sense? You'll need to modify BaseCPU::takeOverFrom() in src/cpu/base.cc to do that, if that is the issue you're having. Look at the lines "if (!ic->isConnected()) {" and "if (!dc->isConnected()) {".
My patches are very old now and I haven't kept them up-to-date, so unfortunately they won't work on the latest version of the repository.
Cheers Tim On 11/12/11 06:32, Malek Musleh wrote:
Hi Timothy, My name is Malek Musleh and I am a PhD Student in ECE at Purdue University. I have been using the Gem5 simulator, and I am trying to implement statistical sampling technique like that of SMARTS. Searching the mailing list, I came across your thread: http://www.mail-archive.com/[email protected]/msg07124.html which seems to sort of describe a similar issue to what I am facing. I am having some issues when I switch back and from Timing CPU to Atomic (the first switch from Atomic -> Timing works of course), and running through a debugger, the error seems to be related to ICache. I am curious to see how you ended up fixing it, as well as other similar related issues with the back/forth switching mechanism. Thanks. Malek
-- Timothy M. Jones http://www.cl.cam.ac.uk/~tmj32 _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
