Hi As the prefetcher initiate with this line: assert(!miss_mshr && !write_mshr);
the question is, what does prefetch on miss mean then? In another word, the gem5 prefetcher can initiate a prefetch request on a read miss. Now when a miss occur, an MSHR entry is allocated for that event. However With that assertion, the prefetcher is unable to initiate a prefetch request because miss_mshr queue is not empty. Can someone clarify that? thanks -- // Naderan *Mahmood; _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
