Hi, that is something as follows: basically it prioritizes the demand misses and writeback requests in the miss-mshr and write-mshr respectively first...but whenever it finds both the queues as empty, it dequeues a prefetch request from the prefetch queue into miss_mshr and generate the bus request for that prefetch request subsequently. But everytime mshr will keep track of all in-flight request, irrespective of it is demand request/prefetch request sent to the bus. Prefetch-on-miss parameter is somewhat orthogonal to it, it basically drives the core to queue a prefetch request to the prefetch queue only in case of a demand miss.
On 12/17/11, Mahmood Naderan wrote: > Hi, > Yesterday, I asked a question about prefetch on miss. However have not > get any answer yet. As you also questioned and andswered about gem5 > prefetcher, we can mesh our minds to see what does gem5 actually do. > > The simulator says it can prefetch on misses. However based on an assertion > line > > assert(!miss_mshr && !write_mshr); > > prefetching only is done when there is no entry in miss mshr and write mshr. > As the mshr tracks misses, it is a strange line. Do you have any comment? > > thanks > -- > // Naderan *Mahmood; _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
