The atomic memory model calculates an estimated latency by summing latencies along the path to get the data. The AtomicSimpleCPU model only does anything with these latencies if the simulate_*_stalls flags are set though, and they are false by default.
Steve On Mon, Jan 2, 2012 at 9:00 AM, David George <[email protected]> wrote: > Hi Chaps, > > As part of my research I'm using gem5 to create a trace of memory reads > and writes from a given binary. To do this, I'm running a simple SPEC2000 > test using caches, and then collecting the trace output from using the > 'Cache' debug flag. > > This then allows me to get access to bus side memory reads and writes > expressed as cache misses, for example: > > 198500: system.cpu.icache: ReadReq (ifetch) 11e40 miss > > This information then gets fed into another set of tools I'm using that > simulate an interconnect between CPU and Memory. > > However, I'm slightly worried that my results are skewed due to M5 > accounting for memory/interconnect latencies in its instruction traces, and > while tying M5 ticks into the model of time for my interconnect simulation, > I need to ensure that I'm not introducing extra memory latency other than > that produced by the interconnect and memory I'm currently modelling > > Is there any way I can configure M5 to assume that memory access latencies > are instant? How does the atomic memory model calculate memory latency for > a given request? > > Or, does anyone know a better way to get a trace of bus side memory > read/write requests that don't take interconnect and memory latencies into > account? > > Thanks in advance! > > Dave George > ______________________________**_________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> >
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
