A plain built of ARM_SE gem5.opt from the gem5 repo, then make checkpoints in the detailed O3 CPU mode with L1 and L2 caches (although the usual case is to make checkpoints with atomic mode which works)
build/ARM_SE/gem5.opt configs/example/se.py --caches --l2cache --cpu-type=detailed --checkpoint-dir=./m5out/checkpoint/ --take-checkpoints 14030000,5000 --max-checkpoints 1 The command manifests with the following segmentation fault. Program received signal SIGSEGV, Segmentation fault. ArmISA::copyRegs (src=0x26e9900, dest=0x2a8d310) at build/ARM_SE/arch/arm/utility.cc:154 154 dest->getITBPtr()->invalidateMiscReg(); Jack Harvard _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
