I wanna change L1 cache bandwidth, but I failed finding information and parameters of the connection between CPU and L1 cache. For main memory, I can just change system bus width and L2 mshr nums, but for L1 cache I wonder if the only way is to change block size of cache.
Thanks. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
